From 139519ef87ceb4ab6c7f0246dd98b002e7bde3f9 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 12 Dec 2006 17:55:27 -0500
Subject: Fix bugs in tlbmap (and thus rangemap since the code is nearly
 identical) Deal with block initializing stores (by doing nothing, at some
 point we might want to do the write hint 64 like thing) Fix tcc instruction
 igoner in legion-lock stuff to be correct in all cases Have console
 interrupts warn rather than panicing until we figure out what to do with
 interrupts

src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
    initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
    fix bug in tlb map code
src/base/range_map.hh:
    fix bug in rangemap code and add range_multimap
    (these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
    fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
    make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
    fix up the rangemap unit test to catch the missing case

--HG--
extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
---
 src/arch/sparc/miscregfile.cc | 20 ++++++++++++++++++++
 src/arch/sparc/miscregfile.hh |  2 ++
 src/arch/sparc/tlb.cc         |  7 +++++--
 src/arch/sparc/tlb_map.hh     | 11 +++++++++--
 4 files changed, 36 insertions(+), 4 deletions(-)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index fd20a14c1..dbcd91925 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -129,6 +129,26 @@ void MiscRegFile::clear()
 MiscReg MiscRegFile::readReg(int miscReg)
 {
     switch (miscReg) {
+      case MISCREG_TLB_DATA:
+        /* Package up all the data for the tlb:
+         * 6666555555555544444444443333333333222222222211111111110000000000
+         * 3210987654321098765432109876543210987654321098765432109876543210
+         *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
+         *                                                           ||||^red
+         *                                                           |||^priv
+         *                                                           ||^am
+         *                                                           |^lsuim
+         *                                                           ^lsudm
+         */
+        return bits((uint64_t)hpstate,2,2) |
+               bits((uint64_t)hpstate,5,5) << 1 |
+               bits((uint64_t)pstate,3,2) << 2 |
+               bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+               bits((uint64_t)partId,7,0) << 8 |
+               bits((uint64_t)tl,2,0) << 16 |
+               (uint64_t)priContext << 32 |
+               (uint64_t)secContext << 48;
+
       case MISCREG_Y:
         return y;
       case MISCREG_CCR:
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index d09005795..c879fd357 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -137,6 +137,8 @@ namespace SparcISA
         MISCREG_QUEUE_NRES_ERROR_HEAD,
         MISCREG_QUEUE_NRES_ERROR_TAIL,
 
+        /* All the data for the TLB packed up in one register. */
+        MISCREG_TLB_DATA,
         MISCREG_NUMMISCREGS
     };
 
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index b0fc562ac..bc5527f2f 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -446,8 +446,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     bool real = false;
     Addr vaddr = req->getVaddr();
     Addr size = req->getSize();
-    ContextType ct;
-    int context;
+    ContextType ct = Primary;
+    int context = 0;
     ASI asi;
 
     TlbEntry *e;
@@ -508,6 +508,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
             panic("Block ASIs not supported\n");
         if (AsiIsNoFault(asi))
             panic("No Fault ASIs not supported\n");
+        if (write && asi == ASI_LDTX_P)
+            // block init store (like write hint64)
+            goto continueDtbFlow;
         if (AsiIsTwin(asi))
             panic("Twin ASIs not supported\n");
         if (AsiIsPartialStore(asi))
diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh
index 226ef23a1..688daf5b9 100644
--- a/src/arch/sparc/tlb_map.hh
+++ b/src/arch/sparc/tlb_map.hh
@@ -53,8 +53,15 @@ class TlbMap
         i = tree.upper_bound(r);
 
         if (i == tree.begin())
-            // Nothing could match, so return end()
-            return tree.end();
+            if (r.real == i->first.real &&
+                r.partitionId == i->first.partitionId &&
+                i->first.va < r.va + r.size &&
+                i->first.va+i->first.size >= r.va &&
+                (r.real || r.contextId == i->first.contextId))
+                return i;
+            else
+                // Nothing could match, so return end()
+                return tree.end();
 
         i--;
 
-- 
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