From 166da650a3c864b31193ade893ed99e547c67644 Mon Sep 17 00:00:00 2001
From: Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
Date: Wed, 5 Apr 2017 13:24:23 -0500
Subject: arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/sparc/faults.cc    | 6 ++++++
 src/arch/sparc/faults.hh    | 1 +
 src/arch/sparc/isa/base.isa | 5 +++++
 3 files changed, 12 insertions(+)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index c09bd0da2..13e9c19f6 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -108,6 +108,12 @@ template<> SparcFaultBase::FaultVals
     SparcFault<FpDisabled>::vals =
 {"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
 
+/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
+ * as a separate part. Therefore, we use the same code and TT */
+template<> SparcFaultBase::FaultVals
+    SparcFault<VecDisabled>::vals =
+{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+
 template<> SparcFaultBase::FaultVals
     SparcFault<FpExceptionIEEE754>::vals =
 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 42c8b7149..aa270fa31 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -122,6 +122,7 @@ class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
 // class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
 
 class FpDisabled : public SparcFault<FpDisabled> {};
+class VecDisabled : public SparcFault<VecDisabled> {};
 
 class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
 
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index b517d462c..4b61c940c 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -578,6 +578,11 @@ output exec {{
             return NoFault;
         }
     }
+    static inline Fault
+    checkVecEnableFault(CPU_EXEC_CONTEXT *xc)
+    {
+        return std::make_shared<VecDisabled>();
+    }
 }};
 
 
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