From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/arch/sparc/isa.hh       |  7 +++++++
 src/arch/sparc/registers.hh | 10 ++++++++--
 src/arch/sparc/utility.cc   |  3 +++
 3 files changed, 18 insertions(+), 2 deletions(-)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 86092f3b5..e6f023bc0 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -206,6 +206,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    // dummy
+    int
+    flattenCCIndex(int reg)
+    {
+        return reg;
+    }
+
     typedef SparcISAParams Params;
     const Params *params() const;
 
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 0e774b69e..b25f34584 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -48,6 +48,10 @@ typedef uint64_t IntReg;
 typedef uint64_t MiscReg;
 typedef float FloatReg;
 typedef uint32_t FloatRegBits;
+
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
 typedef union
 {
     IntReg intReg;
@@ -70,14 +74,16 @@ const int SyscallPseudoReturnReg = 9;
 
 const int NumIntArchRegs = 32;
 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+const int NumCCRegs = 0;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
 // These enumerate all the registers for dependence tracking.
 enum DependenceTags {
     FP_Reg_Base = NumIntRegs,
-    Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
-    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
+    CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
+    Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs,
 };
 
 } // namespace SparcISA
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index d99ef4aa0..9fa102c6a 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -234,6 +234,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
         dest->setFloatRegBits(i, src->readFloatRegBits(i));
     }
 
+    // Would need to add condition-code regs if implemented
+    assert(NumCCRegs == 0);
+
     // Copy misc. registers
     copyMiscRegs(src, dest);
 
-- 
cgit v1.2.3