From 1b1495930c74bab639f0985c2d55f767336aa59b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 24 Oct 2006 15:50:41 -0400
Subject: Replace the Alpha No op with a SPARC one.
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
---
src/arch/sparc/isa_traits.hh | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 6d5aa4251..de54e168b 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -57,12 +57,11 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
- // Alpha Does NOT have a delay slot
+ // SPARC have a delay slot
#define ISA_HAS_DELAY_SLOT 1
- //TODO this needs to be a SPARC Noop
- // Alpha UNOP (ldq_u r31,0(r0))
- const MachInst NoopMachInst = 0x2ffe0000;
+ // SPARC NOP (sethi %(hi(0), g0)
+ const MachInst NoopMachInst = 0x01000000;
const int NumIntRegs = 32;
const int NumFloatRegs = 64;
--
cgit v1.2.3
From e2eef8859b44dbb9d307f6ff50047bdb6b730277 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Oct 2006 17:49:41 -0400
Subject: Implemented the SPARC fill and spill handlers.
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
---
src/arch/sparc/faults.cc | 173 +++++++++++++++++++++++++++++++++++++++++++++-
src/arch/sparc/faults.hh | 6 +-
src/arch/sparc/process.cc | 106 ++++++++++++++++++++++++++--
src/arch/sparc/process.hh | 9 +++
4 files changed, 284 insertions(+), 10 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 7b7765935..fd91ccf0f 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -29,15 +29,22 @@
* Kevin Lim
*/
+#include <algorithm>
+
#include "arch/sparc/faults.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/base.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/process.hh"
+#include "base/bitfield.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
-#include "sim/process.hh"
#include "mem/page_table.hh"
+#include "sim/process.hh"
#endif
+using namespace std;
+
namespace SparcISA
{
@@ -229,6 +236,129 @@ FaultPriority PageTableFault::_priority = 0;
FaultStat PageTableFault::_count;
#endif
+/**
+ * This sets everything up for a normal trap except for actually jumping to
+ * the handler. It will need to be expanded to include the state machine in
+ * the manual. Right now it assumes that traps will always be to the
+ * privileged level.
+ */
+
+void doNormalFault(ThreadContext *tc, TrapType tt)
+{
+ uint64_t TL = tc->readMiscReg(MISCREG_TL);
+ uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
+ uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+ uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+ uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
+ uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
+ uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
+ uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
+ uint64_t GL = tc->readMiscReg(MISCREG_GL);
+ uint64_t PC = tc->readPC();
+ uint64_t NPC = tc->readNextPC();
+
+ //Increment the trap level
+ TL++;
+ tc->setMiscReg(MISCREG_TL, TL);
+
+ //Save off state
+
+ //set TSTATE.gl to gl
+ replaceBits(TSTATE, 42, 40, GL);
+ //set TSTATE.ccr to ccr
+ replaceBits(TSTATE, 39, 32, CCR);
+ //set TSTATE.asi to asi
+ replaceBits(TSTATE, 31, 24, ASI);
+ //set TSTATE.pstate to pstate
+ replaceBits(TSTATE, 20, 8, PSTATE);
+ //set TSTATE.cwp to cwp
+ replaceBits(TSTATE, 4, 0, CWP);
+
+ //Write back TSTATE
+ tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+
+ //set TPC to PC
+ tc->setMiscReg(MISCREG_TPC, PC);
+ //set TNPC to NPC
+ tc->setMiscReg(MISCREG_TNPC, NPC);
+
+ //set HTSTATE.hpstate to hpstate
+ tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+
+ //TT = trap type;
+ tc->setMiscReg(MISCREG_TT, tt);
+
+ //Update the global register level
+ if(1/*We're delivering the trap in priveleged mode*/)
+ tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
+ else
+ tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
+
+ //PSTATE.mm is unchanged
+ //PSTATE.pef = whether or not an fpu is present
+ //XXX We'll say there's one present, even though there aren't
+ //implementations for a decent number of the instructions
+ PSTATE |= (1 << 4);
+ //PSTATE.am = 0
+ PSTATE &= ~(1 << 3);
+ if(1/*We're delivering the trap in priveleged mode*/)
+ {
+ //PSTATE.priv = 1
+ PSTATE |= (1 << 2);
+ //PSTATE.cle = PSTATE.tle
+ replaceBits(PSTATE, 9, 9, PSTATE >> 8);
+ }
+ else
+ {
+ //PSTATE.priv = 0
+ PSTATE &= ~(1 << 2);
+ //PSTATE.cle = 0
+ PSTATE &= ~(1 << 9);
+ }
+ //PSTATE.ie = 0
+ PSTATE &= ~(1 << 1);
+ //PSTATE.tle is unchanged
+ //PSTATE.tct = 0
+ //XXX Where exactly is this field?
+ tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+
+ if(0/*We're delivering the trap in hyperprivileged mode*/)
+ {
+ //HPSTATE.red = 0
+ HPSTATE &= ~(1 << 5);
+ //HPSTATE.hpriv = 1
+ HPSTATE |= (1 << 2);
+ //HPSTATE.ibe = 0
+ HPSTATE &= ~(1 << 10);
+ //HPSTATE.tlz is unchanged
+ tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+ }
+
+ bool changedCWP = true;
+ if(tt == 0x24)
+ {
+ warn("Incrementing the CWP by 1\n");
+ CWP++;
+ }
+ else if(0x80 <= tt && tt <= 0xbf)
+ {
+ warn("Incrementing the CWP by %d\n", CANSAVE + 2);
+ CWP += (CANSAVE + 2);
+ }
+ else if(0xc0 <= tt && tt <= 0xff)
+ {
+ warn("Decrementing the CWP by 1\n");
+ CWP--;
+ }
+ else
+ changedCWP = false;
+ if(changedCWP)
+ {
+ CWP = (CWP + NWindows) % NWindows;
+ tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+ }
+}
+
#if FULL_SYSTEM
void SparcFault::invoke(ThreadContext * tc)
@@ -263,6 +393,42 @@ void TrapInstruction::invoke(ThreadContext * tc)
// Should be handled in ISA.
}
+void SpillNNormal::invoke(ThreadContext *tc)
+{
+ warn("I'm in a spill trap\n");
+ doNormalFault(tc, trapType());
+
+ Process *p = tc->getProcessPtr();
+
+ //This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
+
+ //Then adjust the PC and NPC
+ Addr spillStart = lp->readSpillStart();
+ tc->setPC(spillStart);
+ tc->setNextPC(spillStart + sizeof(MachInst));
+ tc->setNextNPC(spillStart + 2*sizeof(MachInst));
+}
+
+void FillNNormal::invoke(ThreadContext *tc)
+{
+ warn("I'm in a fill trap\n");
+ doNormalFault(tc, trapType());
+
+ Process * p = tc->getProcessPtr();
+
+ //This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
+
+ //The adjust the PC and NPC
+ Addr fillStart = lp->readFillStart();
+ tc->setPC(fillStart);
+ tc->setNextPC(fillStart + sizeof(MachInst));
+ tc->setNextNPC(fillStart + 2*sizeof(MachInst));
+}
+
void PageTableFault::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
@@ -282,6 +448,7 @@ void PageTableFault::invoke(ThreadContext *tc)
FaultBase::invoke(tc);
}
}
+
#endif
} // namespace SparcISA
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index b279f4911..394a06294 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -39,8 +39,8 @@
namespace SparcISA
{
-typedef const uint32_t TrapType;
-typedef const uint32_t FaultPriority;
+typedef uint32_t TrapType;
+typedef uint32_t FaultPriority;
class SparcFault : public FaultBase
{
@@ -547,6 +547,7 @@ class SpillNNormal : public EnumeratedFault
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
+ void invoke(ThreadContext * tc);
};
class SpillNOther : public EnumeratedFault
@@ -577,6 +578,7 @@ class FillNNormal : public EnumeratedFault
FaultName name() {return _name;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
+ void invoke(ThreadContext * tc);
};
class FillNOther : public EnumeratedFault
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 3323ba7a0..a3b7dde7c 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -66,6 +66,10 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
+
+ //Initialize these to 0s
+ fillStart = 0;
+ spillStart = 0;
}
void
@@ -88,15 +92,19 @@ SparcLiveProcess::startup()
*/
//No windows contain info from other programs
- threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
+ threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
//There are no windows to pop
- threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
+ threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
//All windows are available to save into
- threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
+ threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
//All windows are "clean"
- threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
+ threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
//Start with register window 0
- threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
+ threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
+ //Always use spill and fill traps 0
+ threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
+ //Set the trap level to 0
+ threadContexts[0]->setMiscReg(MISCREG_TL, 0);
}
m5_auxv_t buildAuxVect(int64_t type, int64_t val)
@@ -107,6 +115,83 @@ m5_auxv_t buildAuxVect(int64_t type, int64_t val)
return result;
}
+//We only use 19 instructions for the trap handlers, but there would be
+//space for 32 in a real SPARC trap table.
+const int numFillInsts = 32;
+const int numSpillInsts = 32;
+
+MachInst fillHandler[numFillInsts] =
+{
+ htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0
+ htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1
+ htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2
+ htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3
+ htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4
+ htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5
+ htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6
+ htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7
+ htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0
+ htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1
+ htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2
+ htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3
+ htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4
+ htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5
+ htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6
+ htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7
+ htog(0x83880000), //restored
+ htog(0x83F00000), //retry
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000) //illtrap
+};
+
+MachInst spillHandler[numSpillInsts] =
+{
+ htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi
+ htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi
+ htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi
+ htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi
+ htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi
+ htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi
+ htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi
+ htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi
+ htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi
+ htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi
+ htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi
+ htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi
+ htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi
+ htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi
+ htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi
+ htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi
+ htog(0x81880000), //saved
+ htog(0x83F00000), //retry
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000), //illtrap
+ htog(0x00000000) //illtrap
+};
+
void
SparcLiveProcess::argsInit(int intSize, int pageSize)
{
@@ -317,6 +402,17 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+ //Stuff the trap handlers into the processes address space.
+ //Since the stack grows down and is the highest area in the processes
+ //address space, we can put stuff above it and stay out of the way.
+ int fillSize = sizeof(MachInst) * numFillInsts;
+ int spillSize = sizeof(MachInst) * numSpillInsts;
+ fillStart = stack_base;
+ spillStart = fillStart + fillSize;
+ initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize);
+ initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize);
+
+ //Set up the thread context to start running the process
threadContexts[0]->setIntReg(ArgumentReg0, argc);
threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index 7cc52e241..2320810c7 100644
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -55,6 +55,9 @@ class SparcLiveProcess : public LiveProcess
static const Addr StackBias = 2047;
+ //The locations of the fill and spill handlers
+ Addr fillStart, spillStart;
+
std::vector<m5_auxv_t> auxv;
SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
@@ -71,6 +74,12 @@ class SparcLiveProcess : public LiveProcess
void argsInit(int intSize, int pageSize);
+ Addr readFillStart()
+ { return fillStart; }
+
+ Addr readSpillStart()
+ { return spillStart; }
+
};
#endif // __SPARC_PROCESS_HH__
--
cgit v1.2.3
From 047455625e333f10c73d16d5457d5b966ffae8e2 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Oct 2006 17:50:39 -0400
Subject: Fixed the bitfield FCN to include the right bits.
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
---
src/arch/sparc/isa/bitfields.isa | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index 372f5c4ef..7e884866c 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -50,7 +50,7 @@ def bitfield D16LO <13:0>;
def bitfield DISP19 <18:0>;
def bitfield DISP22 <21:0>;
def bitfield DISP30 <29:0>;
-def bitfield FCN <29:26>;
+def bitfield FCN <29:25>;
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
--
cgit v1.2.3
From 99d9d40e6c3e4c6c4fbfa3f4475ac3907e6f9d15 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Oct 2006 17:54:14 -0400
Subject: Implemented the saved and restored instructions, fixed up register
window instructions so that the cwp is modified at the correct time (when
handling the fault), and fixed the "done" instruction.
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
---
src/arch/sparc/isa/decoder.isa | 68 ++++++++++++++++++++++++++----------------
1 file changed, 42 insertions(+), 26 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 45d3616d9..d5f0a0738 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -425,8 +425,24 @@ decode OP default Unknown::unknown()
xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
}});
0x31: decode FCN {
- 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
- 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
+ 0x0: Priv::saved({{
+ assert(Cansave < NWindows - 2);
+ assert(Otherwin || Canrestore);
+ Cansave = Cansave + 1;
+ if(Otherwin == 0)
+ Canrestore = Canrestore - 1;
+ else
+ Otherwin = Otherwin - 1;
+ }});
+ 0x1: BasicOperate::restored({{
+ assert(Cansave || Otherwin);
+ assert(Canrestore < NWindows - 2);
+ Canrestore = Canrestore + 1;
+ if(Otherwin == 0)
+ Cansave = Cansave - 1;
+ else
+ Otherwin = Otherwin - 1;
+ }});
}
0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv
@@ -684,10 +700,6 @@ decode OP default Unknown::unknown()
NNPC = target;
if(fault == NoFault)
{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0)
{
if(Otherwin)
@@ -697,14 +709,18 @@ decode OP default Unknown::unknown()
}
else
{
- Rd = Rs1 + Rs2_or_imm13;
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ Cwp = (Cwp - 1 + NWindows) % NWindows;
Cansave = Cansave + 1;
Canrestore = Canrestore - 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
+ warn("About to set the CWP to %d\n", Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
}});
0x3A: decode CC
@@ -747,11 +763,11 @@ decode OP default Unknown::unknown()
fault = new SpillNOther(Wstate<5:3>);
else
fault = new SpillNNormal(Wstate<2:0>);
- Cwp = (Cwp + 2) % NWindows;
+ //Cwp = (Cwp + 2) % NWindows;
}
else if(Cleanwin - Canrestore == 0)
{
- Cwp = (Cwp + 1) % NWindows;
+ //Cwp = (Cwp + 1) % NWindows;
fault = new CleanWindow;
}
else
@@ -760,17 +776,13 @@ decode OP default Unknown::unknown()
Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave - 1;
Canrestore = Canrestore + 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3D: restore({{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0)
{
if(Otherwin)
@@ -780,14 +792,18 @@ decode OP default Unknown::unknown()
}
else
{
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ Cwp = (Cwp - 1 + NWindows) % NWindows;
Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave + 1;
Canrestore = Canrestore - 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3E: decode FCN {
0x0: Priv::done({{
@@ -812,7 +828,7 @@ decode OP default Unknown::unknown()
Ccr = Tstate<39:32>;
Gl = Tstate<42:40>;
NPC = Tpc;
- NNPC = Tnpc + 4;
+ NNPC = Tnpc;
Tl = Tl - 1;
}});
}
--
cgit v1.2.3
From 93b3176d4e72813bc64340eb534eb280f68764e1 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Oct 2006 17:58:44 -0400
Subject: Fixed the priv instruction format.
src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
---
src/arch/sparc/isa/formats/priv.isa | 5 ++---
src/arch/sparc/isa/operands.isa | 21 +++++++++++----------
2 files changed, 13 insertions(+), 13 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 2a38422a7..04c67d332 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -121,15 +121,14 @@ let {{
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
- checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
- ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
+ checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
}};
def format HPriv(code, *opt_flags) {{
- checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
+ checkCode = "!Hpstate<2:2>"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index b8b75170b..ba2c38e91 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -95,18 +95,19 @@ def operands {{
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
+ 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
- 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
+ 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
+ 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
+ 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
+ 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
+ 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
+ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
- 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
--
cgit v1.2.3
From e441be1b82171651308c22eac01c854e7813c2dd Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Oct 2006 20:22:23 -0400
Subject: Change the default function from setMiscRegWithEffect to setMiscReg
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
---
src/arch/sparc/miscregfile.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 8041e45c0..efaa22f67 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -470,7 +470,7 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
/** Floating Point Status Register */
case MISCREG_FSR:
- panic("Floating Point not implemented\n");
+ setReg(miscReg, val);
default:
#if FULL_SYSTEM
setFSRegWithEffect(miscReg, val, tc);
--
cgit v1.2.3
From 5024b202785b066307b5bc697ee39bccf344a100 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Oct 2006 20:23:00 -0400
Subject: Got rid of some debug output
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
---
src/arch/sparc/faults.cc | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index fd91ccf0f..2c8da44c5 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -336,22 +336,14 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
bool changedCWP = true;
if(tt == 0x24)
- {
- warn("Incrementing the CWP by 1\n");
CWP++;
- }
else if(0x80 <= tt && tt <= 0xbf)
- {
- warn("Incrementing the CWP by %d\n", CANSAVE + 2);
CWP += (CANSAVE + 2);
- }
else if(0xc0 <= tt && tt <= 0xff)
- {
- warn("Decrementing the CWP by 1\n");
CWP--;
- }
else
changedCWP = false;
+
if(changedCWP)
{
CWP = (CWP + NWindows) % NWindows;
@@ -395,7 +387,6 @@ void TrapInstruction::invoke(ThreadContext * tc)
void SpillNNormal::invoke(ThreadContext *tc)
{
- warn("I'm in a spill trap\n");
doNormalFault(tc, trapType());
Process *p = tc->getProcessPtr();
@@ -413,7 +404,6 @@ void SpillNNormal::invoke(ThreadContext *tc)
void FillNNormal::invoke(ThreadContext *tc)
{
- warn("I'm in a fill trap\n");
doNormalFault(tc, trapType());
Process * p = tc->getProcessPtr();
--
cgit v1.2.3
From d1b30102fdaa79b9937e9405aeade54a72685746 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Oct 2006 20:24:01 -0400
Subject: Changed the number of register windows to be more realistic.
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
---
src/arch/sparc/isa_traits.hh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index de54e168b..fb09121a3 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -86,7 +86,7 @@ namespace SparcISA
const int MaxPGL = 2;
// NWINDOWS - number of register windows, can be 3 to 32
- const int NWindows = 32;
+ const int NWindows = 8;
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
--
cgit v1.2.3
From f33bab2386ea1f3dbdcff547501af0e78d659101 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Oct 2006 22:47:17 -0400
Subject: Cleaned up the decoder slightly.
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
---
src/arch/sparc/isa/decoder.isa | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index d5f0a0738..a2657b3cd 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -447,12 +447,12 @@ decode OP default Unknown::unknown()
0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv
// access
- fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+ xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
}});
0x33: HPriv::wrhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
- fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+ xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
}});
0x34: decode OPF{
format BasicOperate{
@@ -719,7 +719,6 @@ decode OP default Unknown::unknown()
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
- warn("About to set the CWP to %d\n", Cwp);
}
}
}});
--
cgit v1.2.3
From 2cb190d1e3854f3d82b88ccd9b6b6365b87c331d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Oct 2006 22:48:02 -0400
Subject: Reorganized the MiscRegFile
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
---
src/arch/sparc/miscregfile.cc | 163 +++++++++++++-----------------------------
src/arch/sparc/miscregfile.hh | 1 -
2 files changed, 49 insertions(+), 115 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index efaa22f67..ada3c18e7 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -221,8 +221,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg,
}
return tc->getCpuPtr()->curCycle() - tickFields.counter |
tickFields.npt << 63;
- case MISCREG_PC:
- return tc->readPC();
case MISCREG_FPRS:
fault = new UnimpFault("FPU not implemented\n");
return 0;
@@ -280,112 +278,115 @@ Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
switch (miscReg) {
case MISCREG_Y:
y = val;
- return NoFault;
+ break;
case MISCREG_CCR:
ccr = val;
- return NoFault;
+ break;
case MISCREG_ASI:
asi = val;
- return NoFault;
+ break;
case MISCREG_FPRS:
fprs = val;
- return NoFault;
+ break;
case MISCREG_TICK:
- tick = val;
- return NoFault;
+ tick = val;
+ break;
case MISCREG_PCR:
case MISCREG_PIC:
panic("ASR number %d not implemented\n", miscReg - AsrStart);
case MISCREG_GSR:
gsr = val;
+ break;
case MISCREG_SOFTINT:
- softint = val;
- return NoFault;
+ softint = val;
+ break;
case MISCREG_TICK_CMPR:
- tick_cmpr = val;
- return NoFault;
+ tick_cmpr = val;
+ break;
case MISCREG_STICK:
- stick = val;
- return NoFault;
+ stick = val;
+ break;
case MISCREG_STICK_CMPR:
- stick_cmpr = val;
- return NoFault;
+ stick_cmpr = val;
+ break;
/** Privilged Registers */
case MISCREG_TPC:
tpc[tl-1] = val;
- return NoFault;
+ break;
case MISCREG_TNPC:
tnpc[tl-1] = val;
- return NoFault;
+ break;
case MISCREG_TSTATE:
tstate[tl-1] = val;
- return NoFault;
+ break;
case MISCREG_TT:
tt[tl-1] = val;
- return NoFault;
+ break;
case MISCREG_PRIVTICK:
panic("Priviliged access to tick regesiters not implemented\n");
case MISCREG_TBA:
- tba = val;
- return NoFault;
+ // clear lower 7 bits on writes.
+ tba = val & ULL(~0x7FFF);
+ break;
case MISCREG_PSTATE:
pstate = val;
- return NoFault;
+ break;
case MISCREG_TL:
tl = val;
- return NoFault;
+ break;
case MISCREG_PIL:
pil = val;
- return NoFault;
+ break;
case MISCREG_CWP:
cwp = val;
- return NoFault;
+ break;
case MISCREG_CANSAVE:
cansave = val;
- return NoFault;
+ break;
case MISCREG_CANRESTORE:
canrestore = val;
- return NoFault;
+ break;
case MISCREG_CLEANWIN:
cleanwin = val;
- return NoFault;
+ break;
case MISCREG_OTHERWIN:
otherwin = val;
- return NoFault;
+ break;
case MISCREG_WSTATE:
wstate = val;
- return NoFault;
+ break;
case MISCREG_GL:
gl = val;
- return NoFault;
+ break;
/** Hyper privileged registers */
case MISCREG_HPSTATE:
hpstate = val;
- return NoFault;
+ break;
case MISCREG_HTSTATE:
htstate[tl-1] = val;
- return NoFault;
+ break;
case MISCREG_HINTP:
panic("HINTP not implemented\n");
case MISCREG_HTBA:
htba = val;
- return NoFault;
+ break;
case MISCREG_STRAND_STS_REG:
strandStatusReg = val;
- return NoFault;
+ break;
case MISCREG_HSTICK_CMPR:
hstick_cmpr = val;
- return NoFault;
+ break;
/** Floating Point Status Register */
case MISCREG_FSR:
fsr = val;
- return NoFault;
+ break;
default:
panic("Miscellaneous register %d not implemented\n", miscReg);
}
+ return NoFault;
}
Fault MiscRegFile::setRegWithEffect(int miscReg,
@@ -393,91 +394,25 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
{
const uint64_t Bit64 = (1ULL << 63);
switch (miscReg) {
- case MISCREG_Y:
- case MISCREG_CCR:
- case MISCREG_ASI:
- setReg(miscReg, val);
- return NoFault;
- case MISCREG_PRIVTICK:
case MISCREG_TICK:
- if (isNonPriv())
- return new PrivilegedOpcode;
- if (isPriv())
- return new PrivilegedAction;
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
tickFields.npt = val & Bit64 ? 1 : 0;
- return NoFault;
- case MISCREG_PC:
- return new IllegalInstruction;
+ break;
case MISCREG_FPRS:
- return new UnimpFault("FPU not implemented\n");
+ //Configure the fpu based on the fprs
+ break;
case MISCREG_PCR:
- return new UnimpFault("Performance Instrumentation not impl\n");
- case MISCREG_PIC:
- return new UnimpFault("Performance Instrumentation not impl\n");
- case MISCREG_GSR:
- return setReg(miscReg, val);
-
- /** Privilged Registers */
- case MISCREG_TPC:
- case MISCREG_TNPC:
- case MISCREG_TSTATE:
- case MISCREG_TT:
- if (tl == 0)
- return new IllegalInstruction;
- setReg(miscReg, val);
- return NoFault;
-
- case MISCREG_TBA:
- // clear lower 7 bits on writes.
- setReg(miscReg, val & ULL(~0x7FFF));
- return NoFault;
-
- case MISCREG_PSTATE:
- setReg(miscReg, val);
- return NoFault;
-
- case MISCREG_TL:
- if (isHyperPriv() && val > MaxTL)
- setReg(miscReg, MaxTL);
- else if (isPriv() && !isHyperPriv() && val > MaxPTL)
- setReg(miscReg, MaxPTL);
- else
- setReg(miscReg, val);
- return NoFault;
-
+ //Set up performance counting based on pcr value
+ break;
case MISCREG_CWP:
tc->changeRegFileContext(CONTEXT_CWP, val);
- case MISCREG_CANSAVE:
- case MISCREG_CANRESTORE:
- case MISCREG_CLEANWIN:
- case MISCREG_OTHERWIN:
- case MISCREG_WSTATE:
- setReg(miscReg, val);
- return NoFault;
-
+ break;
case MISCREG_GL:
- int newval;
- if (isHyperPriv() && val > MaxGL)
- newval = MaxGL;
- else if (isPriv() && !isHyperPriv() && val > MaxPGL)
- newval = MaxPGL;
- else
- newval = val;
- tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
- setReg(miscReg, newval);
- return NoFault;
-
- /** Floating Point Status Register */
- case MISCREG_FSR:
- setReg(miscReg, val);
- default:
-#if FULL_SYSTEM
- setFSRegWithEffect(miscReg, val, tc);
-#else
- return new IllegalInstruction;
-#endif
+ tc->changeRegFileContext(CONTEXT_GLOBALS, val);
+ break;
}
+ setReg(miscReg, val);
+ return NoFault;
}
void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index be143311f..0d81dae1e 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -56,7 +56,6 @@ namespace SparcISA
MISCREG_CCR = AsrStart + 2,
MISCREG_ASI = AsrStart + 3,
MISCREG_TICK = AsrStart + 4,
- MISCREG_PC = AsrStart + 5,
MISCREG_FPRS = AsrStart + 6,
MISCREG_PCR = AsrStart + 16,
MISCREG_PIC = AsrStart + 17,
--
cgit v1.2.3
From 944bfde6b34a27f2438e38f7d870532ed6c0447a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 27 Oct 2006 01:36:42 -0400
Subject: Clean up MiscRegFile
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
---
src/arch/sparc/miscregfile.cc | 65 ++++---------------------------------------
src/arch/sparc/miscregfile.hh | 28 ++++---------------
2 files changed, 11 insertions(+), 82 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index ada3c18e7..bf4572878 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -202,78 +202,27 @@ MiscReg MiscRegFile::readReg(int miscReg)
}
}
-MiscReg MiscRegFile::readRegWithEffect(int miscReg,
- Fault &fault, ThreadContext * tc)
+MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
{
- fault = NoFault;
switch (miscReg) {
- case MISCREG_Y:
- case MISCREG_CCR:
- case MISCREG_ASI:
- return readReg(miscReg);
-
case MISCREG_TICK:
case MISCREG_PRIVTICK:
- // Check for reading privilege
- if (tickFields.npt && !isNonPriv()) {
- fault = new PrivilegedAction;
- return 0;
- }
return tc->getCpuPtr()->curCycle() - tickFields.counter |
tickFields.npt << 63;
case MISCREG_FPRS:
- fault = new UnimpFault("FPU not implemented\n");
- return 0;
+ panic("FPU not implemented\n");
case MISCREG_PCR:
- fault = new UnimpFault("Performance Instrumentation not impl\n");
- return 0;
case MISCREG_PIC:
- fault = new UnimpFault("Performance Instrumentation not impl\n");
- return 0;
- case MISCREG_GSR:
- return readReg(miscReg);
-
- /** Privilged Registers */
- case MISCREG_TPC:
- case MISCREG_TNPC:
- case MISCREG_TSTATE:
- case MISCREG_TT:
- if (tl == 0) {
- fault = new IllegalInstruction;
- return 0;
- } // NOTE THE FALL THROUGH!
- case MISCREG_PSTATE:
- case MISCREG_TL:
- return readReg(miscReg);
-
- case MISCREG_TBA:
- return readReg(miscReg) & ULL(~0x7FFF);
-
- case MISCREG_PIL:
-
- case MISCREG_CWP:
- case MISCREG_CANSAVE:
- case MISCREG_CANRESTORE:
- case MISCREG_CLEANWIN:
- case MISCREG_OTHERWIN:
- case MISCREG_WSTATE:
- case MISCREG_GL:
- return readReg(miscReg);
+ panic("Performance Instrumentation not impl\n");
/** Floating Point Status Register */
case MISCREG_FSR:
panic("Floating Point not implemented\n");
- default:
-#if FULL_SYSTEM
- return readFSRegWithEffect(miscReg, fault, tc);
-#else
- fault = new IllegalInstruction;
- return 0;
-#endif
}
+ return readReg(miscReg);
}
-Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
+void MiscRegFile::setReg(int miscReg, const MiscReg &val)
{
switch (miscReg) {
case MISCREG_Y:
@@ -386,10 +335,9 @@ Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
default:
panic("Miscellaneous register %d not implemented\n", miscReg);
}
- return NoFault;
}
-Fault MiscRegFile::setRegWithEffect(int miscReg,
+void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
const uint64_t Bit64 = (1ULL << 63);
@@ -412,7 +360,6 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
break;
}
setReg(miscReg, val);
- return NoFault;
}
void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 0d81dae1e..771cb1ed6 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -365,31 +365,13 @@ namespace SparcISA
reset();
}
- /** read a value out of an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial. */
MiscReg readReg(int miscReg);
- /** Read a value from an IPR. Only the SE iprs are here and the rest
- * are are readFSRegWithEffect (which is called by readRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
-
- /** write a value into an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial.*/
- Fault setReg(int miscReg, const MiscReg &val);
-
- /** Write a value into an IPR. Only the SE iprs are here and the rest
- * are are setFSRegWithEffect (which is called by setRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- Fault setRegWithEffect(int miscReg,
+ MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+
+ void setReg(int miscReg, const MiscReg &val);
+
+ void setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc);
void serialize(std::ostream & os);
--
cgit v1.2.3
From b1cc98ed54b21e02c5ac52002497a5368452c529 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 27 Oct 2006 01:43:26 -0400
Subject: Made the regfile compatible with the new definitions in MiscRegFile
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
---
src/arch/sparc/regfile.cc | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 747426781..5eb874d39 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -82,18 +82,21 @@ MiscReg RegFile::readMiscReg(int miscReg)
MiscReg RegFile::readMiscRegWithEffect(int miscReg,
Fault &fault, ThreadContext *tc)
{
- return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+ fault = NoFault;
+ return miscRegFile.readRegWithEffect(miscReg, tc);
}
Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
{
- return miscRegFile.setReg(miscReg, val);
+ miscRegFile.setReg(miscReg, val);
+ return NoFault;
}
Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, tc);
+ miscRegFile.setRegWithEffect(miscReg, val, tc);
+ return NoFault;
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
--
cgit v1.2.3
From 709d50cd6bb4571b13385eed578f419bef3d579c Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 27 Oct 2006 01:43:51 -0400
Subject: Got rid of some outdated comments.
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
---
src/arch/sparc/isa/decoder.isa | 4 ----
1 file changed, 4 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index a2657b3cd..dc7597e5e 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -357,13 +357,9 @@ decode OP default Unknown::unknown()
}});
}
0x29: HPriv::rdhpr({{
- // XXX Need to protect with format that traps non-priv/priv
- // access
Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
}});
0x2A: Priv::rdpr({{
- // XXX Need to protect with format that traps non-priv
- // access
Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
}});
0x2B: BasicOperate::flushw({{
--
cgit v1.2.3
From 6dddca951151c953fdab6f3e57b9385150d8b90b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 01:58:37 -0500
Subject: Add an integer microcode register.
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
---
src/arch/sparc/intregfile.cc | 19 ++++++++++++++++---
src/arch/sparc/intregfile.hh | 1 +
src/arch/sparc/isa/operands.isa | 1 +
src/arch/sparc/isa_traits.hh | 8 ++++++--
4 files changed, 24 insertions(+), 5 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index bef62f6ae..164f194dd 100644
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -75,8 +75,14 @@ IntRegFile::IntRegFile()
IntReg IntRegFile::readReg(int intReg)
{
- IntReg val =
- regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
+ IntReg val;
+ if(intReg < NumRegularIntRegs)
+ val = regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
+ else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs)
+ val = microRegs[intReg];
+ else
+ panic("Tried to read non-existant integer register\n");
+
DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
return val;
}
@@ -86,7 +92,12 @@ Fault IntRegFile::setReg(int intReg, const IntReg &val)
if(intReg)
{
DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
- regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
+ if(intReg < NumRegularIntRegs)
+ regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
+ else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs)
+ microRegs[intReg] = val;
+ else
+ panic("Tried to set non-existant integer register\n");
}
return NoFault;
}
@@ -123,6 +134,7 @@ void IntRegFile::serialize(std::ostream &os)
SERIALIZE_ARRAY(regGlobals[x], RegsPerFrame);
for(x = 0; x < 2 * NWindows; x++)
SERIALIZE_ARRAY(regSegments[x], RegsPerFrame);
+ SERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
}
void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
@@ -132,4 +144,5 @@ void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
UNSERIALIZE_ARRAY(regGlobals[x], RegsPerFrame);
for(unsigned int x = 0; x < 2 * NWindows; x++)
UNSERIALIZE_ARRAY(regSegments[x], RegsPerFrame);
+ UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
}
diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
index d305c753b..223e3b34c 100644
--- a/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@ -65,6 +65,7 @@ namespace SparcISA
IntReg regGlobals[MaxGL][RegsPerFrame];
IntReg regSegments[2 * NWindows][RegsPerFrame];
+ IntReg microRegs[NumMicroIntRegs];
enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index ba2c38e91..80b499b91 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -61,6 +61,7 @@ def operands {{
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
+ 'uReg0': ('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6),
'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd.
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index fb09121a3..46a0ebbfb 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -57,13 +57,17 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
- // SPARC have a delay slot
+ // SPARC has a delay slot
#define ISA_HAS_DELAY_SLOT 1
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
- const int NumIntRegs = 32;
+ const int NumRegularIntRegs = 32;
+ const int NumMicroIntRegs = 1;
+ const int NumIntRegs =
+ NumRegularIntRegs +
+ NumMicroIntRegs;
const int NumFloatRegs = 64;
const int NumMiscRegs = 40;
--
cgit v1.2.3
From ce313a15d5310aa8ee4412014e129ae26e7d18dc Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 01:59:30 -0500
Subject: Fixed ldstub to use the right format, and made the load/store
operations use the integer microcode register.
--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
---
src/arch/sparc/isa/decoder.isa | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index dc7597e5e..aa3b6de6f 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -851,16 +851,15 @@ decode OP default Unknown::unknown()
0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
- 0x0D: ldstub({{
- Rd = Mem.ub;
- Mem.ub = 0xFF;
- }});
}
+ 0x0D: LoadStore::ldstub(
+ {{Rd = Mem.ub;}},
+ {{Mem.ub = 0xFF;}});
0x0E: Store::stx({{Mem.udw = Rd}});
0x0F: LoadStore::swap(
- {{*temp = Rd.uw;
+ {{uReg0 = Rd.uw;
Rd.uw = Mem.uw;}},
- {{Mem.uw = *temp;}});
+ {{Mem.uw = uReg0;}});
format Load {
0x10: lduwa({{Rd = Mem.uw;}});
0x11: lduba({{Rd = Mem.ub;}});
@@ -888,9 +887,9 @@ decode OP default Unknown::unknown()
{{Mem.ub = 0xFF}});
0x1E: Store::stxa({{Mem.udw = Rd}});
0x1F: LoadStore::swapa(
- {{*temp = Rd.uw;
+ {{uReg0 = Rd.uw;
Rd.uw = Mem.uw;}},
- {{Mem.uw = *temp;}});
+ {{Mem.uw = uReg0;}});
format Trap {
0x20: Load::ldf({{Frd.uw = Mem.uw;}});
0x21: decode X {
--
cgit v1.2.3
From 9adba8d98e0d73a6dcf745258da3ac2272e93a6a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 02:57:32 -0500
Subject: Bring casa and casxa up to date
src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
---
src/arch/sparc/isa/decoder.isa | 22 ++++++++--------
src/arch/sparc/isa/formats/formats.isa | 3 ---
src/arch/sparc/isa/formats/mem/basicmem.isa | 2 +-
src/arch/sparc/isa/formats/mem/blockmem.isa | 2 +-
src/arch/sparc/isa/formats/mem/mem.isa | 2 +-
src/arch/sparc/isa/formats/mem/util.isa | 40 ++++++++++++++++++-----------
6 files changed, 40 insertions(+), 31 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index aa3b6de6f..a64ff09bb 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1072,19 +1072,21 @@ decode OP default Unknown::unknown()
{{fault = new DataAccessException;}});
}
}
- 0x3C: Cas::casa({{
- uint64_t val = Mem.uw;
- if(Rs2.uw == val)
+ 0x3C: Cas::casa(
+ {{uReg0 = Mem.uw;}},
+ {{if(Rs2.uw == uReg0)
Mem.uw = Rd.uw;
- Rd.uw = val;
- }});
+ else
+ storeCond = false;
+ Rd.uw = uReg0;}});
0x3D: Nop::prefetcha({{ }});
- 0x3E: Cas::casxa({{
- uint64_t val = Mem.udw;
- if(Rs2 == val)
+ 0x3E: Cas::casxa(
+ {{uReg0 = Mem.udw;}},
+ {{if(Rs2 == uReg0)
Mem.udw = Rd;
- Rd = val;
- }});
+ else
+ storeCond = false;
+ Rd = uReg0;}});
}
}
}
diff --git a/src/arch/sparc/isa/formats/formats.isa b/src/arch/sparc/isa/formats/formats.isa
index 5b81a1ab1..8125e6349 100644
--- a/src/arch/sparc/isa/formats/formats.isa
+++ b/src/arch/sparc/isa/formats/formats.isa
@@ -42,9 +42,6 @@
//Include the memory formats
##include "mem/mem.isa"
-//Include the compare and swap format
-##include "cas.isa"
-
//Include the trap format
##include "trap.isa"
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index c13194d0f..147767bbc 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -156,7 +156,7 @@ let {{
header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)
- exec_output = doSplitExecute(code, addrCalcReg, addrCalcImm, execute,
+ exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, execute,
faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags)
return (header_output, decoder_output, exec_output, decode_block)
}};
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 93ad1b2b8..4f2f30236 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -301,7 +301,7 @@ let {{
"set_flags": flag_code})
decoder_output += BlockMemMicroConstructor.subst(iop)
decoder_output += BlockMemMicroConstructor.subst(iop_imm)
- exec_output += doSplitExecute(
+ exec_output += doDualSplitExecute(
pcedCode, addrCalcReg, addrCalcImm, execute, faultCode,
makeMicroName(name, microPc),
makeMicroName(name + "Imm", microPc),
diff --git a/src/arch/sparc/isa/formats/mem/mem.isa b/src/arch/sparc/isa/formats/mem/mem.isa
index 20a22c45d..fedece2b8 100644
--- a/src/arch/sparc/isa/formats/mem/mem.isa
+++ b/src/arch/sparc/isa/formats/mem/mem.isa
@@ -41,5 +41,5 @@
//Include the block memory format
##include "blockmem.isa"
-//Include the load/store memory format
+//Include the load/store and cas memory format
##include "loadstore.isa"
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 241a25d17..673aee6be 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -102,6 +102,9 @@ def template StoreExecute {{
{
Fault fault = NoFault;
uint64_t write_result = 0;
+ //This is to support the conditional store in cas instructions.
+ //It should be optomized out in all the others
+ bool storeCond = true;
Addr EA;
%(op_decl)s;
%(op_rd)s;
@@ -112,7 +115,7 @@ def template StoreExecute {{
{
%(code)s;
}
- if(fault == NoFault)
+ if(storeCond && fault == NoFault)
{
fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
}
@@ -130,6 +133,7 @@ def template StoreExecute {{
{
Fault fault = NoFault;
uint64_t write_result = 0;
+ bool storeCond = true;
Addr EA;
%(op_decl)s;
%(op_rd)s;
@@ -140,7 +144,7 @@ def template StoreExecute {{
{
%(code)s;
}
- if(fault == NoFault)
+ if(storeCond && fault == NoFault)
{
fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
}
@@ -204,23 +208,29 @@ let {{
//and in the other they're distributed across two. Also note that for
//execute functions, the name of the base class doesn't matter.
let {{
- def doSplitExecute(code, eaRegCode, eaImmCode, execute,
+ def doSplitExecute(code, eaCode, execute,
+ faultCode, name, Name, opt_flags):
+ codeIop = InstObjParams(name, Name, '', code, opt_flags)
+ eaIop = InstObjParams(name, Name, '', eaCode,
+ opt_flags, {"fault_check": faultCode})
+ iop = InstObjParams(name, Name, '', code, opt_flags,
+ {"fault_check": faultCode, "ea_code" : eaCode})
+ (iop.ea_decl,
+ iop.ea_rd,
+ iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
+ (iop.code_decl,
+ iop.code_rd,
+ iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
+ return execute.subst(iop)
+
+
+ def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags):
- codeIop = InstObjParams(nameReg, NameReg, '', code, opt_flags)
executeCode = ''
for (eaCode, name, Name) in (
(eaRegCode, nameReg, NameReg),
(eaImmCode, nameImm, NameImm)):
- eaIop = InstObjParams(name, Name, '', eaCode,
- opt_flags, {"fault_check": faultCode})
- iop = InstObjParams(name, Name, '', code, opt_flags,
- {"fault_check": faultCode, "ea_code" : eaCode})
- (iop.ea_decl,
- iop.ea_rd,
- iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
- (iop.code_decl,
- iop.code_rd,
- iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
- executeCode += execute.subst(iop)
+ executeCode += doSplitExecute(code, eaCode,
+ execute, faultCode, name, Name, opt_flags)
return executeCode
}};
--
cgit v1.2.3
From 6e66de7c7563ef7e969a0df4a9a09d026231baa5 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 03:26:41 -0500
Subject: Fix when the IsDelayedCommit flag is set.
--HG--
extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
---
src/arch/sparc/isa/formats/mem/blockmem.isa | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 4f2f30236..8b4aca473 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -56,14 +56,14 @@ output header {{
{}
};
- class BlockMemMicro : public SparcDelayedMicroInst
+ class BlockMemMicro : public SparcMicroInst
{
protected:
// Constructor
BlockMemMicro(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, int8_t _offset) :
- SparcDelayedMicroInst(mnem, _machInst, __opClass),
+ SparcMicroInst(mnem, _machInst, __opClass),
offset(_offset)
{}
@@ -290,6 +290,8 @@ let {{
flag_code = ''
if (microPc == 7):
flag_code = "flags[IsLastMicroOp] = true;"
+ else:
+ flag_code = "flags[IsDelayedCommit] = true;"
pcedCode = matcher.sub("Frd_%d" % microPc, code)
iop = InstObjParams(name, Name, 'BlockMem', pcedCode,
opt_flags, {"ea_code": addrCalcReg,
--
cgit v1.2.3
From 349c7aff9b1a4643f8501d4b5cd7eff8753dfac9 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 03:40:52 -0500
Subject: Move the mem classes into util.isa so that multiple inheritance can
be used in the future for micro insts.
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
---
src/arch/sparc/isa/formats/mem/basicmem.isa | 94 -----------------------------
src/arch/sparc/isa/formats/mem/util.isa | 94 +++++++++++++++++++++++++++++
2 files changed, 94 insertions(+), 94 deletions(-)
(limited to 'src/arch/sparc')
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 147767bbc..cb6c2f161 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -32,100 +32,6 @@
// Mem instructions
//
-output header {{
- /**
- * Base class for memory operations.
- */
- class Mem : public SparcStaticInst
- {
- protected:
-
- // Constructor
- Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Class for memory operations which use an immediate offset.
- */
- class MemImm : public Mem
- {
- protected:
-
- // Constructor
- MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
- {}
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- const int32_t imm;
- };
-}};
-
-output decoder {{
- std::string Mem::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- bool load = flags[IsLoad];
- bool save = flags[IsStore];
-
- printMnemonic(response, mnemonic);
- if(save)
- {
- printReg(response, _srcRegIdx[0]);
- ccprintf(response, ", ");
- }
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
- ccprintf(response, " + ");
- printReg(response, _srcRegIdx[!save ? 1 : 2]);
- ccprintf(response, " ]");
- if(load)
- {
- ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-
- std::string MemImm::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- bool load = flags[IsLoad];
- bool save = flags[IsStore];
-
- printMnemonic(response, mnemonic);
- if(save)
- {
- printReg(response, _srcRegIdx[0]);
- ccprintf(response, ", ");
- }
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
- if(imm >= 0)
- ccprintf(response, " + 0x%x ]", imm);
- else
- ccprintf(response, " + -0x%x ]", -imm);
- if(load)
- {
- ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-}};
-
def template MemDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 673aee6be..b9f7fde2d 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -33,6 +33,100 @@
// Mem utility templates and functions
//
+output header {{
+ /**
+ * Base class for memory operations.
+ */
+ class Mem : public SparcStaticInst
+ {
+ protected:
+
+ // Constructor
+ Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ SparcStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Class for memory operations which use an immediate offset.
+ */
+ class MemImm : public Mem
+ {
+ protected:
+
+ // Constructor
+ MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
+ {}
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ const int32_t imm;
+ };
+}};
+
+output decoder {{
+ std::string Mem::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = flags[IsLoad];
+ bool save = flags[IsStore];
+
+ printMnemonic(response, mnemonic);
+ if(save)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ ccprintf(response, " + ");
+ printReg(response, _srcRegIdx[!save ? 1 : 2]);
+ ccprintf(response, " ]");
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string MemImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = flags[IsLoad];
+ bool save = flags[IsStore];
+
+ printMnemonic(response, mnemonic);
+ if(save)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ if(imm >= 0)
+ ccprintf(response, " + 0x%x ]", imm);
+ else
+ ccprintf(response, " + -0x%x ]", -imm);
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+}};
+
//This template provides the execute functions for a load
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
--
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