From ce18d900a17cdda2cc041b51c56e6c84fb155331 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 13 Mar 2007 16:13:21 +0000 Subject: Replaced makeExtMI with predecode. Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d --- src/arch/sparc/utility.hh | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 64b91695e..4b662b5ac 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -48,9 +48,15 @@ namespace SparcISA tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2))); } - inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { - ExtMachInst emi = (MachInst) inst; + enum PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + inline unsigned int + predecode(ExtMachInst &emi, Addr currPC, MachInst inst, + ThreadContext * xc) { + emi = inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is //slightly redundant, but it removes the need to put a condition @@ -61,7 +67,7 @@ namespace SparcISA else emi |= (static_cast(bits(inst, 12, 5)) << (sizeof(MachInst) * 8)); - return emi; + return MoreBytes | ExtMIReady; } inline bool isCallerSaveIntegerRegister(unsigned int reg) { -- cgit v1.2.3 From a2b56088fb4d12aee73ecfeaba88cfa46f98567e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 15 Mar 2007 02:47:42 +0000 Subject: Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86 --- src/arch/sparc/predecoder.hh | 112 +++++++++++++++++++++++++++++++++++++++++++ src/arch/sparc/utility.hh | 22 --------- 2 files changed, 112 insertions(+), 22 deletions(-) create mode 100644 src/arch/sparc/predecoder.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh new file mode 100644 index 000000000..71b14b020 --- /dev/null +++ b/src/arch/sparc/predecoder.hh @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_PREDECODER_HH__ +#define __ARCH_SPARC_PREDECODER_HH__ + +#include "arch/sparc/types.hh" +#include "base/misc.hh" +#include "sim/host.hh" + +class ThreadContext; + +namespace SparcISA +{ + class Predecoder + { + protected: + ThreadContext * tc; + //The extended machine instruction being generated + ExtMachInst emi; + + public: + Predecoder(ThreadContext * _tc) : tc(_tc) + {} + + ThreadContext * getTC() + { + return tc; + } + + void setTC(ThreadContext * _tc) + { + tc = _tc; + } + + void process() + { + } + + //Use this to give data to the predecoder. This should be used + //when there is control flow. + void moreBytes(Addr currPC, Addr off, MachInst inst) + { + assert(off == 0); + + emi = inst; + //The I bit, bit 13, is used to figure out where the ASI + //should come from. Use that in the ExtMachInst. This is + //slightly redundant, but it removes the need to put a condition + //into all the execute functions + if(inst & (1 << 13)) + emi |= (static_cast( + tc->readMiscRegNoEffect(MISCREG_ASI)) + << (sizeof(MachInst) * 8)); + else + emi |= (static_cast(bits(inst, 12, 5)) + << (sizeof(MachInst) * 8)); + } + + //Use this to give data to the predecoder. This should be used + //when instructions are executed in order. + void moreBytes(MachInst machInst) + { + moreBytes(0, 0, machInst); + } + + bool needMoreBytes() + { + return true; + } + + bool extMachInstReady() + { + return true; + } + + //This returns a constant reference to the ExtMachInst to avoid a copy + const ExtMachInst & getExtMachInst() + { + return emi; + } + }; +}; + +#endif // __ARCH_SPARC_PREDECODER_HH__ diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 4b662b5ac..278b39fb7 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -48,28 +48,6 @@ namespace SparcISA tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2))); } - enum PredecodeResult { - MoreBytes = 1, - ExtMIReady = 2 - }; - - inline unsigned int - predecode(ExtMachInst &emi, Addr currPC, MachInst inst, - ThreadContext * xc) { - emi = inst; - //The I bit, bit 13, is used to figure out where the ASI - //should come from. Use that in the ExtMachInst. This is - //slightly redundant, but it removes the need to put a condition - //into all the execute functions - if(inst & (1 << 13)) - emi |= (static_cast(xc->readMiscRegNoEffect(MISCREG_ASI)) - << (sizeof(MachInst) * 8)); - else - emi |= (static_cast(bits(inst, 12, 5)) - << (sizeof(MachInst) * 8)); - return MoreBytes | ExtMIReady; - } - inline bool isCallerSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); return false; -- cgit v1.2.3