From 5bd07f98ed8b69e93345df4a7e626376fab57d8a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 14 Aug 2006 19:25:07 -0400 Subject: Fix up doxygen. --HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2 --- src/arch/sparc/ua2005.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index b89d48663..6493ddfd5 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -37,7 +37,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, int64_t time; SparcSystem *sys; switch (miscReg) { - /** Full system only ASRs */ + /* Full system only ASRs */ case MISCREG_SOFTINT: if (isNonPriv()) return new PrivilegedOpcode; @@ -94,7 +94,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, sTickCompare.schedule(time * Clock::Int::ns); return NoFault; - /** Fullsystem only Priv registers. */ + /* Fullsystem only Priv registers. */ case MISCREG_PIL: if (FULL_SYSTEM) { setReg(miscReg, val); @@ -104,7 +104,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } else panic("PIL not implemented for syscall emulation\n"); - /** Hyper privileged registers */ + /* Hyper privileged registers */ case MISCREG_HPSTATE: case MISCREG_HINTP: setReg(miscReg, val); @@ -147,7 +147,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) { switch (miscReg) { - /** Privileged registers. */ + /* Privileged registers. */ case MISCREG_SOFTINT: if (isNonPriv()) { fault = new PrivilegedOpcode; @@ -177,7 +177,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) return readReg(miscReg); - /** Hyper privileged registers */ + /* Hyper privileged registers */ case MISCREG_HPSTATE: case MISCREG_HINTP: return readReg(miscReg); -- cgit v1.2.3