From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/arch/sparc/isa.hh       | 7 +++++++
 src/arch/sparc/registers.hh | 9 ++++++++-
 src/arch/sparc/utility.cc   | 3 +++
 3 files changed, 18 insertions(+), 1 deletion(-)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 1d2a457d2..51e797c90 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -211,6 +211,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    // dummy
+    int
+    flattenVectorIndex(int reg) const
+    {
+        return reg;
+    }
+
     int
     flattenMiscIndex(int reg) const
     {
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index b25f34584..a59139ba2 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -51,6 +51,11 @@ typedef uint32_t FloatRegBits;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
+// vector register file entry type
+typedef uint64_t VectorRegElement;
+const int NumVectorRegElements = 0;
+const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
+typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
 
 typedef union
 {
@@ -75,6 +80,7 @@ const int SyscallPseudoReturnReg = 9;
 const int NumIntArchRegs = 32;
 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
 const int NumCCRegs = 0;
+const int NumVectorRegs = 0;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
@@ -82,7 +88,8 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 enum DependenceTags {
     FP_Reg_Base = NumIntRegs,
     CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
-    Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+    Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+    Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs, // NumVectorRegs == 0
     Max_Reg_Index = Misc_Reg_Base + NumMiscRegs,
 };
 
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 34d4f79b3..6d7a1ba95 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -237,6 +237,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     // Would need to add condition-code regs if implemented
     assert(NumCCRegs == 0);
 
+    // Copy vector registers when vector registers put to use.
+    assert(NumVectorRegs == 0);
+
     // Copy misc. registers
     copyMiscRegs(src, dest);
 
-- 
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