From 729dbb60e918dbe08339ab6cc89917c3d8e24f26 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 17 Dec 2006 11:15:37 -0500
Subject: Added in the extended twin load format

src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
---
 src/arch/sparc/isa/decoder.isa              | 12 ++++++
 src/arch/sparc/isa/formats/mem/blockmem.isa | 60 ++++++++++++++++++++++++++++-
 2 files changed, 71 insertions(+), 1 deletion(-)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 01fe32ef7..bbc6a8c4b 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1126,6 +1126,18 @@ decode OP default Unknown::unknown()
                     0x15: FailUnimpl::lddfa_real_io();
                     //ASI_REAL_IO_LITTLE
                     0x1D: FailUnimpl::lddfa_real_io_l();
+                    //ASI_LDTX_REAL
+                    0x26: TwinLoad::ldtx_real(
+                        {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                    //ASI_LDTX_N
+                    0x27: TwinLoad::ldtx_n(
+                        {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                    //ASI_LDTX_REAL_L
+                    0x2E: TwinLoad::ldtx_real_l(
+                        {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                    //ASI_LDTX_N_L
+                    0x2F: TwinLoad::ldtx_n_l(
+                        {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
                     //ASI_PRIMARY
                     0x80: FailUnimpl::lddfa_p();
                     //ASI_PRIMARY_LITTLE
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index fcd61a5b4..8bbbdc1da 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -208,6 +208,64 @@ output decoder {{
 
 }};
 
+output decoder {{
+        std::string TwinMemMicro::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+            std::stringstream response;
+            bool load = flags[IsLoad];
+            bool save = flags[IsStore];
+
+            printMnemonic(response, mnemonic);
+            if(save)
+            {
+                printReg(response, _srcRegIdx[0]);
+                ccprintf(response, ", ");
+            }
+            ccprintf(response, "[ ");
+            printReg(response, _srcRegIdx[!save ? 0 : 1]);
+            ccprintf(response, " + ");
+            printReg(response, _srcRegIdx[!save ? 1 : 2]);
+            ccprintf(response, " ]");
+            if(load)
+            {
+                ccprintf(response, ", ");
+                printReg(response, _destRegIdx[0]);
+            }
+
+            return response.str();
+        }
+
+        std::string TwinMemImmMicro::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+            std::stringstream response;
+            bool load = flags[IsLoad];
+            bool save = flags[IsStore];
+
+            printMnemonic(response, mnemonic);
+            if(save)
+            {
+                printReg(response, _srcRegIdx[1]);
+                ccprintf(response, ", ");
+            }
+            ccprintf(response, "[ ");
+            printReg(response, _srcRegIdx[0]);
+            if(imm >= 0)
+                ccprintf(response, " + 0x%x ]", imm);
+            else
+                ccprintf(response, " + -0x%x ]", -imm);
+            if(load)
+            {
+                ccprintf(response, ", ");
+                printReg(response, _destRegIdx[0]);
+            }
+
+            return response.str();
+        }
+
+}};
+
 def template BlockMemDeclare {{
         /**
          * Static instruction class for a block memory operation
@@ -447,7 +505,7 @@ let {{
             decoder_output += BlockMemMicroConstructor.subst(iop)
             decoder_output += BlockMemMicroConstructor.subst(iop_imm)
             exec_output += doDualSplitExecute(
-                    pcedCode, addrCalcReg, addrCalcImm, execute, faultCode,
+                    pcedCode, addrCalcReg, addrCalcImm, LoadExecute, faultCode,
                     makeMicroName(name, microPc),
                     makeMicroName(name + "Imm", microPc),
                     makeMicroName(Name, microPc),
-- 
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