From 7846f59d0dcb36c13e06a3ba8a4c461e646582b6 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 3 Jun 2013 13:55:41 +0200 Subject: arch: Create a method to finalize physical addresses in the TLB Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations. --- src/arch/sparc/tlb.cc | 6 ++++++ src/arch/sparc/tlb.hh | 1 + 2 files changed, 7 insertions(+) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 5d6dfe2c3..66e75a98a 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -848,6 +848,12 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) return NoFault; } +Fault +TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +{ + return NoFault; +} + Cycles TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 7246cd4f6..e084f665c 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -169,6 +169,7 @@ class TLB : public BaseTLB * does not support the Checker model at the moment */ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt); Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt); void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); -- cgit v1.2.3