From 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:30 -0600 Subject: arch, cpu: Add support for flattening misc register indexes. With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects. --- src/arch/sparc/isa.hh | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index e6f023bc0..31cb09c7e 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -177,7 +177,6 @@ class ISA : public SimObject using SimObject::startup; protected: - bool isHyperPriv() { return hpstate.hpriv; } bool isPriv() { return hpstate.hpriv || pstate.priv; } bool isNonPriv() { return !isPriv(); } @@ -213,6 +212,13 @@ class ISA : public SimObject return reg; } + int + flattenMiscIndex(int reg) + { + return reg; + } + + typedef SparcISAParams Params; const Params *params() const; -- cgit v1.2.3