From 9f75c1c58f8352a8625f035c151ebcf6ce95b908 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 11 Jan 2007 09:29:03 -0500 Subject: ua2005.cc: i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. src/arch/sparc/ua2005.cc: i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. --HG-- extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff --- src/arch/sparc/ua2005.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index c153c2d52..128402fdd 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -24,8 +24,6 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi */ #include "arch/sparc/miscregfile.hh" @@ -81,7 +79,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_PSTATE: - if (val & ie && !(pstate & ie)) { + if (val & PSTATE::ie && !(pstate & PSTATE::ie)) { tc->getCpuPtr()->checkInterrupts = true; } setReg(miscReg, val); @@ -128,7 +126,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 - setReg(miscReg, val | id); + setReg(miscReg, val | HPSTATE::id); break; case MISCREG_HTSTATE: case MISCREG_STRAND_STS_REG: -- cgit v1.2.3