From a5cb9b51be92aee6d925652b1994233dbc42f05c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Jan 2007 22:46:01 -0500 Subject: Fix the FCMPCC bitfield. --HG-- extra : convert_revision : d2c538e7f469bd12a80eb8585c78d5325d6e6141 --- src/arch/sparc/isa/bitfields.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa index 7e884866c..e75680d2b 100644 --- a/src/arch/sparc/isa/bitfields.isa +++ b/src/arch/sparc/isa/bitfields.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -38,7 +38,7 @@ def bitfield A <29>; def bitfield BPCC <21:20>; // for BPcc & FBPcc -def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa +def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa def bitfield FMOVCC <13:11>; // for FMOVcc def bitfield CC <12:11>; // for MOVcc & Tcc def bitfield MOVCC3 <18>; // also for MOVcc -- cgit v1.2.3 From 1f7db14dd4374d83549db395a6ba477452a25b10 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Jan 2007 22:52:54 -0500 Subject: Add implementation for the fcmp instructions. These don't behave -quite- right with respect to quite NaNs, but hopefully we don't need to worry about the distinction. --HG-- extra : convert_revision : 67b6583a20530b7a393aa04d0b71031d3c72ecdd --- src/arch/sparc/isa/decoder.isa | 64 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index f8f381b65..d9c8286f8 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -734,7 +734,69 @@ decode OP default Unknown::unknown() default: FailUnimpl::fpop1(); } } - 0x35: Trap::fpop2({{fault = new FpDisabled;}}); + 0x35: decode OPF{ + format BasicOperate{ + 0x51: fcmps({{ + uint8_t fcc; + if(isnan(Frs1s) || isnan(Frs2s)) + fcc = 3; + else if(Frs1s < Frs2s) + fcc = 1; + else if(Frs1s > Frs2s) + fcc = 2; + else + fcc = 0; + uint8_t firstbit = 10; + if(FCMPCC) + firstbit = FCMPCC * 2 + 30; + Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); + }}); + 0x52: fcmpd({{ + uint8_t fcc; + if(isnan(Frs1s) || isnan(Frs2s)) + fcc = 3; + else if(Frs1s < Frs2s) + fcc = 1; + else if(Frs1s > Frs2s) + fcc = 2; + else + fcc = 0; + uint8_t firstbit = 10; + if(FCMPCC) + firstbit = FCMPCC * 2 + 30; + Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); + }}); + 0x53: Trap::fcmpq({{fault = new FpExceptionOther;}}); + 0x54: fcmpes({{ + uint8_t fcc = 0; + if(isnan(Frs1s) || isnan(Frs2s)) + fault = new FpExceptionIEEE754; + if(Frs1s < Frs2s) + fcc = 1; + else if(Frs1s > Frs2s) + fcc = 2; + uint8_t firstbit = 10; + if(FCMPCC) + firstbit = FCMPCC * 2 + 30; + Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); + }}); + 0x55: fcmped({{ + uint8_t fcc = 0; + if(isnan(Frs1s) || isnan(Frs2s)) + fault = new FpExceptionIEEE754; + if(Frs1s < Frs2s) + fcc = 1; + else if(Frs1s > Frs2s) + fcc = 2; + uint8_t firstbit = 10; + if(FCMPCC) + firstbit = FCMPCC * 2 + 30; + Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); + }}); + 0x56: Trap::fcmpeq({{fault = new FpExceptionOther;}}); + default: FailUnimpl::fpop2(); + } + } //This used to be just impdep1, but now it's a whole bunch //of instructions 0x36: decode OPF{ -- cgit v1.2.3 From 4a16ea95c1134d0709670559a96c171b33421db8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Jan 2007 22:54:28 -0500 Subject: Fix the Frs?s operands to use single width by default, rather than double width. --HG-- extra : convert_revision : 36137ee025dc5c79665b041b43bd89505715ca70 --- src/arch/sparc/isa/operands.isa | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 2d1c3d3b9..140055010 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -88,9 +88,9 @@ def operands {{ 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), - 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), + 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), - 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), + 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), -- cgit v1.2.3