From b2eecd643c1706d0d070568d5370aafa3910c104 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Nov 2006 17:11:10 -0500 Subject: Add support for mmapped iprs to atomic cpu src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits --HG-- extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115 --- src/arch/sparc/asi.hh | 2 +- src/arch/sparc/miscregfile.hh | 1 - src/arch/sparc/mmaped_ipr.hh | 63 +++++++++++++++++++++++++++++++++++++++++++ src/arch/sparc/tlb.cc | 24 ++++++++++++++--- src/arch/sparc/tlb.hh | 3 +++ 5 files changed, 88 insertions(+), 5 deletions(-) create mode 100644 src/arch/sparc/mmaped_ipr.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh index bd1696c78..a0d667cf3 100644 --- a/src/arch/sparc/asi.hh +++ b/src/arch/sparc/asi.hh @@ -35,6 +35,7 @@ namespace SparcISA { enum ASI { + ASI_IMPLICIT = 0x00, /* Priveleged ASIs */ //0x00-0x03 implementation dependent ASI_NUCLEUS = 0x4, @@ -242,7 +243,6 @@ namespace SparcISA ASI_BLK_SL = 0xF9, ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL, //0xFA-0xFF implementation dependent - ASI_IMPLICIT = 0xFF, MAX_ASI = 0xFF }; diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index a4ce6ca5c..9cfe3a8cf 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -32,7 +32,6 @@ #ifndef __ARCH_SPARC_MISCREGFILE_HH__ #define __ARCH_SPARC_MISCREGFILE_HH__ -#include "arch/sparc/asi.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/types.hh" diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh new file mode 100644 index 000000000..d87d127b0 --- /dev/null +++ b/src/arch/sparc/mmaped_ipr.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_MMAPED_IPR_HH__ +#define __ARCH_SPARC_MMAPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "cpu/thread_context.hh" +#include "mem/packet.hh" +#include "arch/sparc/tlb.hh" + + +namespace SparcISA +{ +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +} + + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +} + + +} // namespace SparcISA + +#endif diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 9b7943ed9..5fde4d36d 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -508,13 +508,31 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) req->setPaddr(e->pte.paddr() & ~e->pte.size() | req->getVaddr() & e->pte.size()); return NoFault; - /*** End of normal Path ***/ + /** Normal flow ends here. */ -handleMmuRegAccess: handleScratchRegAccess: - panic("How are we ever going to deal with this?\n"); + if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new DataAccessException; + } +handleMmuRegAccess: + req->setMmapedIpr(true); + req->setPaddr(req->getVaddr()); + return NoFault; }; +Tick +DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) +{ + panic("need to implement DTB::doMmuRegRead()\n"); +} + +Tick +DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) +{ + panic("need to implement DTB::doMmuRegWrite()\n"); +} + void TLB::serialize(std::ostream &os) { diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 824d6494c..2df4fe4c8 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -38,6 +38,7 @@ #include "sim/sim_object.hh" class ThreadContext; +class Packet; namespace SparcISA { @@ -142,6 +143,8 @@ class DTB : public TLB } Fault translate(RequestPtr &req, ThreadContext *tc, bool write); + Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); + Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); private: void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, -- cgit v1.2.3