From d30e3b30afde1916537f8ebb76cbb9b1d2df6f7d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 10 Nov 2006 15:29:32 -0500
Subject: Added StrandStsReg operand.

--HG--
extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a
---
 src/arch/sparc/isa/operands.isa | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch/sparc')

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index caee20b0c..2d200f568 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -123,6 +123,7 @@ def operands {{
     'Htba':		('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
     'HstickCmpr':	('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
     'Hver':		('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
+    'StrandStsReg':	('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
 
     'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
     # Mem gets a large number so it's always last
-- 
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