From d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 09:09:56 -0700 Subject: Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. --- src/arch/sparc/SConscript | 2 ++ src/arch/sparc/SparcInterrupts.py | 33 +++++++++++++++++++++++++++++++++ src/arch/sparc/interrupts.cc | 37 +++++++++++++++++++++++++++++++++++++ src/arch/sparc/interrupts.hh | 14 ++++++++++++-- 4 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 src/arch/sparc/SparcInterrupts.py create mode 100644 src/arch/sparc/interrupts.cc (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index d4d68a6bd..126587835 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -52,7 +52,9 @@ if env['TARGET_ISA'] == 'sparc': if env['FULL_SYSTEM']: SimObject('SparcSystem.py') + SimObject('SparcInterrupts.py') + Source('interrupts.cc') Source('stacktrace.cc') Source('system.cc') Source('ua2005.cc') diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py new file mode 100644 index 000000000..2cc964c2d --- /dev/null +++ b/src/arch/sparc/SparcInterrupts.py @@ -0,0 +1,33 @@ +# Copyright (c) 2008 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject + +class SparcInterrupts(SimObject): + type = 'SparcInterrupts' + cxx_class = 'SparcISA::Interrupts' diff --git a/src/arch/sparc/interrupts.cc b/src/arch/sparc/interrupts.cc new file mode 100644 index 000000000..96d61e559 --- /dev/null +++ b/src/arch/sparc/interrupts.cc @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2008 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/sparc/interrupts.hh" + +SparcISA::Interrupts * +SparcInterruptsParams::create() +{ + return new SparcISA::Interrupts(this); +} diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 4ad3385fb..7d1496d8e 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -35,11 +35,13 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "cpu/thread_context.hh" +#include "params/SparcInterrupts.hh" +#include "sim/sim_object.hh" namespace SparcISA { -class Interrupts +class Interrupts : public SimObject { private: @@ -48,7 +50,15 @@ class Interrupts uint64_t intStatus; public: - Interrupts() + typedef SparcInterruptsParams Params; + + const Params * + params() const + { + return dynamic_cast(_params); + } + + Interrupts(Params * p) : SimObject(p) { clear_all(); } -- cgit v1.2.3