From 63fdabf191b8ac1031fb25da61ab2526d4bb6d05 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:48:51 -0500 Subject: make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd --- src/arch/sparc/isa/decoder.isa | 4 ++-- src/arch/sparc/isa/formats/basic.isa | 3 ++- src/arch/sparc/isa/formats/integerop.isa | 6 +++--- src/arch/sparc/isa/includes.isa | 4 +++- src/arch/sparc/isa_traits.hh | 2 +- src/arch/sparc/system.cc | 1 + src/arch/sparc/tlb.cc | 4 +++- src/arch/sparc/utility.hh | 2 +- 8 files changed, 16 insertions(+), 10 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index bd1a44342..bfb8252b9 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -685,8 +685,8 @@ decode OP default Unknown::unknown() Fsr &= ~(0x1F); }}); 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); - 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); - 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); + 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); + 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a4c05387b..9805c7c0b 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -38,6 +38,7 @@ def template BasicExecPanic {{ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); + M5_DUMMY_RETURN } }}; diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 4f8ebebcc..9470fc55f 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -154,7 +154,7 @@ output decoder {{ bool IntOp::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) + if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) { printMnemonic(os, "mov"); printSrcReg(os, 1); @@ -168,7 +168,7 @@ output decoder {{ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or")) + if(!std::strcmp(mnemonic, "or")) { if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) { diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 624afb693..688f26d5c 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -34,6 +34,7 @@ // output header {{ +#include #include #include @@ -64,6 +65,7 @@ output exec {{ #include #endif +#include #include "arch/sparc/asi.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 3f0b9cad5..ea15fac10 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -59,7 +59,7 @@ namespace SparcISA // These enumerate all the registers for dependence tracking. enum DependenceTags { FP_Base_DepTag = 33, - Ctrl_Base_DepTag = 97, + Ctrl_Base_DepTag = 97 }; // semantically meaningful register indices diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index da83d86fc..800d47c15 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -195,6 +195,7 @@ bool SparcSystem::breakpoint() { panic("Need to implement"); + M5_DUMMY_RETURN } void diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 612345300..dc4c9ef1f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -28,6 +28,8 @@ * Authors: Ali Saidi */ +#include + #include "arch/sparc/asi.hh" #include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" @@ -53,7 +55,7 @@ TLB::TLB(const std::string &name, int s) fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); tlb = new TlbEntry[size]; - memset(tlb, 0, sizeof(TlbEntry) * size); + std::memset(tlb, 0, sizeof(TlbEntry) * size); for (int x = 0; x < size; x++) freeList.push_back(&tlb[x]); diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 5c7fe343d..3c8bdcd01 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -50,7 +50,7 @@ namespace SparcISA inline ExtMachInst makeExtMI(MachInst inst, ThreadContext * xc) { - ExtMachInst emi = (unsigned MachInst) inst; + ExtMachInst emi = (MachInst) inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is //slightly redundant, but it removes the need to put a condition -- cgit v1.2.3