From 9ad24e22481665ae626b0e4ed44e2eea91c1b553 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Mar 2007 13:56:09 -0400 Subject: move hver code to ua2005.cc src/arch/sparc/miscregfile.cc: this code should be in readFSreg src/arch/sparc/ua2005.cc: move code froh miscregfile to ua2005.cc --HG-- extra : convert_revision : fa450b04ad73ab6f6e25d66fa0368054263f09f9 --- src/arch/sparc/miscregfile.cc | 8 -------- src/arch/sparc/ua2005.cc | 8 +++++++- 2 files changed, 7 insertions(+), 9 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 20bc4ae5d..f3be1c4c2 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -231,14 +231,6 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return hintp; case MISCREG_HTBA: return htba; - case MISCREG_HVER: - // XXX set to match Legion - return ULL(0x3e) << 48 | - ULL(0x23) << 32 | - ULL(0x20) << 24 | - //MaxGL << 16 | XXX For some reason legion doesn't set GL - MaxTL << 8 | - (NWindows -1) << 0; case MISCREG_STRAND_STS_REG: return strandStatusReg; case MISCREG_HSTICK_CMPR: diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 439f38457..865280038 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -235,7 +235,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) case MISCREG_HTBA: return readRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: - return NWindows | MaxTL << 8 | MaxGL << 16; + // XXX set to match Legion + return ULL(0x3e) << 48 | + ULL(0x23) << 32 | + ULL(0x20) << 24 | + //MaxGL << 16 | XXX For some reason legion doesn't set GL + MaxTL << 8 | + (NWindows -1) << 0; case MISCREG_STRAND_STS_REG: System *sys; -- cgit v1.2.3 From a068d6db0fff7056abb06bb8a99494b63bd169e1 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 13 Mar 2007 00:05:52 -0400 Subject: fix interrupting during a quisce on sparc src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5 --- src/arch/sparc/ua2005.cc | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 865280038..48e97a531 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -195,6 +195,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("No support for setting spec_en bit\n"); setRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { + DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep tc->suspend(); if (tc->getKernelStats()) @@ -307,7 +308,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "stick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { @@ -324,11 +325,15 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) // we're actually at the correct cycle or we need to wait a little while // more int ticks; + if ( tc->status() == ThreadContext::Halted || + tc->status() == ThreadContext::Unallocated) + return; + ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "hstick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { -- cgit v1.2.3