From 3e8e813218e7779a41bc12caae33db5e239506c9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Jul 2009 23:54:56 -0700 Subject: CPU: Separate out native trace into ISA (in)dependent code and SimObjects. --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py --- src/arch/x86/SConscript | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/x86/SConscript') diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 96af0767c..3d1f6f8e3 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -95,6 +95,7 @@ if env['TARGET_ISA'] == 'x86': Source('insts/microregop.cc') Source('insts/static_inst.cc') Source('isa.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('predecoder.cc') Source('predecoder_tables.cc') @@ -102,6 +103,8 @@ if env['TARGET_ISA'] == 'x86': Source('tlb.cc') Source('utility.cc') + SimObject('X86NativeTrace.py') + SimObject('X86TLB.py') TraceFlag('Predecoder', "Predecoder debug output") TraceFlag('X86', "Generic X86 ISA debugging") -- cgit v1.2.3