From f17f3d20be08d25f176138691a29897df54e5cc0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:24 -0800 Subject: X86: Implement a page table walker. --HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec --- src/arch/x86/X86TLB.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/X86TLB.py') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index ce4db4f4c..2d562ba9a 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -53,12 +53,15 @@ # # Authors: Gabe Black -from m5.SimObject import SimObject +from MemObject import MemObject from m5.params import * -class X86TLB(SimObject): + +class X86TLB(MemObject): type = 'X86TLB' abstract = True size = Param.Int("TLB size") + walker_port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") class X86DTB(X86TLB): type = 'X86DTB' -- cgit v1.2.3 From fce45baf178b43c2ea1476967fba3766e9b2ea9d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:31 -0800 Subject: X86: Work on the page table walker, TLB, and related faults. --HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f --- src/arch/x86/X86TLB.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/x86/X86TLB.py') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 2d562ba9a..5c174be59 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -55,6 +55,7 @@ from MemObject import MemObject from m5.params import * +from m5.proxy import * class X86TLB(MemObject): type = 'X86TLB' -- cgit v1.2.3 From 1048b548fabfb7af2113f226f2151d3eb0e63289 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 18:06:57 -0800 Subject: X86: Separate out the page table walker into it's own cc and hh. --HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042 --- src/arch/x86/X86TLB.py | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'src/arch/x86/X86TLB.py') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 5c174be59..dc080f37e 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -54,15 +54,28 @@ # Authors: Gabe Black from MemObject import MemObject +from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5 import build_env -class X86TLB(MemObject): +if build_env['FULL_SYSTEM']: + class X86PagetableWalker(MemObject): + type = 'X86PagetableWalker' + cxx_namespace = 'X86ISA' + cxx_class = 'Walker' + port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") + +class X86TLB(SimObject): type = 'X86TLB' + cxx_namespace = 'X86ISA' + cxx_class = 'TLB' abstract = True size = Param.Int("TLB size") - walker_port = Port("Port for the hardware table walker") - system = Param.System(Parent.any, "system object") + if build_env['FULL_SYSTEM']: + walker = Param.X86PagetableWalker(\ + X86PagetableWalker(), "page table walker") class X86DTB(X86TLB): type = 'X86DTB' -- cgit v1.2.3