From 504f90f76350ce14debfbfa837423144b0abdbe4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 2 Oct 2007 23:00:37 -0700 Subject: X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af --- src/arch/x86/X86TLB.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/x86/X86TLB.py') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index f16408e63..ce4db4f4c 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -58,18 +58,18 @@ from m5.params import * class X86TLB(SimObject): type = 'X86TLB' abstract = True - #size = Param.Int("TLB size") + size = Param.Int("TLB size") class X86DTB(X86TLB): type = 'X86DTB' cxx_namespace = 'X86ISA' cxx_class = 'DTB' - #size = 64 + size = 64 class X86ITB(X86TLB): type = 'X86ITB' cxx_namespace = 'X86ISA' cxx_class = 'ITB' - #size = 64 + size = 64 -- cgit v1.2.3