From be246cef6251113ad25f59cfef37b746c80b11c5 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 3 Mar 2014 14:44:57 +0100 Subject: x86: Setup correct TSL/TR segment attributes on INIT The TSL/LDT & TR/TSS segments didn't contain valid attributes. This caused problems when transfering the state into KVM where invalid state is a no-go. Fixup the attributes with values from AMD's architecture programmer's manual. --- src/arch/x86/faults.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/faults.cc') diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index aa859052e..0cbf2334e 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -245,15 +245,21 @@ namespace X86ISA tc->setMiscReg(MISCREG_IDTR_BASE, 0); tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); + SegAttr tslAttr = 0; + tslAttr.present = 1; + tslAttr.type = 2; // LDT tc->setMiscReg(MISCREG_TSL, 0); tc->setMiscReg(MISCREG_TSL_BASE, 0); tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_TSL_ATTR, 0); + tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); + SegAttr trAttr = 0; + trAttr.present = 1; + trAttr.type = 3; // Busy 16-bit TSS tc->setMiscReg(MISCREG_TR, 0); tc->setMiscReg(MISCREG_TR_BASE, 0); tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_TR_ATTR, 0); + tc->setMiscReg(MISCREG_TR_ATTR, trAttr); // This value should be the family/model/stepping of the processor. // (page 418). It should be consistent with the value from CPUID, but -- cgit v1.2.3