From 247586274724ea9f2a22a87747c9e074870d16a8 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 16 Oct 2014 05:49:44 -0400 Subject: arch,x86,mem: Dynamically determine the ISA for Ruby store check This patch makes the memory system ISA-agnostic by enabling the Ruby Sequencer to dynamically determine if it has to do a store check. To enable this check, the ISA is encoded as an enum, and the system is able to provide the ISA to the Sequencer at run time. --HG-- rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh --- src/arch/x86/insts/microldstop.hh | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'src/arch/x86/insts/microldstop.hh') diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh index 4d96c0ec0..32f3fec04 100644 --- a/src/arch/x86/insts/microldstop.hh +++ b/src/arch/x86/insts/microldstop.hh @@ -41,20 +41,13 @@ #define __ARCH_X86_INSTS_MICROLDSTOP_HH__ #include "arch/x86/insts/microop.hh" +#include "arch/x86/ldstflags.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "sim/faults.hh" namespace X86ISA { - const Request::FlagsType SegmentFlagMask = mask(4); - const int FlagShift = 4; - enum FlagBit { - CPL0FlagBit = 1, - AddrSizeFlagBit = 2, - StoreCheck = 4 - }; - /** * Base class for load and store ops */ -- cgit v1.2.3