From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sun, 26 Jul 2015 10:21:20 -0500 Subject: cpu: implements vector registers This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now. --- src/arch/x86/insts/static_inst.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/arch/x86/insts') diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index 39091289f..49ea6ef4e 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -225,12 +225,19 @@ namespace X86ISA ccprintf(os, "%%cc%d", rel_reg); break; + case VectorRegClass: + ccprintf(os, "%%cc%d", rel_reg); + break; + case MiscRegClass: switch (rel_reg) { default: ccprintf(os, "%%ctrl%d", rel_reg); } break; + + default: + panic("Invalid register class!\n"); } } -- cgit v1.2.3