From ae390c629f2a10fd6a1c2eb50b7d3510d6e091da Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 2 Sep 2019 21:26:12 -0700 Subject: arch: Make a base class for Interrupts. That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/x86/interrupts.hh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/arch/x86/interrupts.hh') diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 519d9f10e..3c383ab92 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -53,13 +53,14 @@ #ifndef __ARCH_X86_INTERRUPTS_HH__ #define __ARCH_X86_INTERRUPTS_HH__ -#include "arch/x86/regs/apic.hh" +#include "arch/generic/interrupts.hh" #include "arch/x86/faults.hh" #include "arch/x86/intmessage.hh" +#include "arch/x86/regs/apic.hh" #include "base/bitfield.hh" #include "cpu/thread_context.hh" -#include "dev/x86/intdev.hh" #include "dev/io_device.hh" +#include "dev/x86/intdev.hh" #include "params/X86LocalApic.hh" #include "sim/eventq.hh" @@ -72,7 +73,7 @@ namespace X86ISA { ApicRegIndex decodeAddr(Addr paddr); -class Interrupts : public SimObject +class Interrupts : public BaseInterrupts { protected: System *sys; -- cgit v1.2.3