From 83f2b253989fd6dfc8f48d5368ae351ade91cfc6 Mon Sep 17 00:00:00 2001 From: Swapnil Haria Date: Mon, 15 Jan 2018 21:49:17 -0600 Subject: arch-x86: Adding clflush, clflushopt, clwb instructions This patch adds support for cache flushing instructions in x86. It piggybacks on support for similar instructions in arm ISA added by Nikos Nikoleris. I have tested each instruction using microbenchmarks. Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d Reviewed-on: https://gem5-review.googlesource.com/7401 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/arch/x86/isa/decoder/two_byte_opcodes.isa | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/isa/decoder/two_byte_opcodes.isa') diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index f0698ce18..aa60e4c48 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -800,8 +800,16 @@ 0x3: Inst::STMXCSR(Md); 0x4: xsave(); 0x5: xrstor(); - 0x6: Inst::UD2(); - 0x7: clflush(); + 0x6: decode LEGACY_DECODEVAL { + 0x0: Inst::UD2(); + 0x1: Inst::CLWB(Mb); + default: Inst::UD2(); + } + 0x7: decode LEGACY_DECODEVAL { + 0x0: Inst::CLFLUSH(Mb); + 0x1: Inst::CLFLUSHOPT(Mb); + default: Inst::CLFLUSH(Mb); + } } } 0x7: Inst::IMUL(Gv,Ev); -- cgit v1.2.3