From 62a2e85c9a0af39970568b35afa4d050ef571b23 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 7 Aug 2009 10:12:58 -0700 Subject: X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend. --- .../data_conversion/endian_conversion.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py') diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py index ac2343462..f6aac1761 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py @@ -64,15 +64,15 @@ def macroop BSWAP_D_R def macroop BSWAP_Q_R { roli reg, reg, 8, dataSize=2 - roli reg, reg, 16, dataSize=4 - roli reg, reg, 8, dataSize=2 - roli reg, reg, 32, dataSize=8 - roli reg, reg, 8, dataSize=2 - roli reg, reg, 16, dataSize=4 - roli reg, reg, 8, dataSize=2 + roli t1, reg, 16, dataSize=4 + # Top 4 bytes of t1 are now zero + roli t1, t1, 8, dataSize=2 + roli t1, t1, 32, dataSize=8 + srli t2, reg, 32, dataSize=8 + roli t2, t2, 8, dataSize=2 + roli t2, t2, 16, dataSize=4 + # Top 4 bytes of t2 are now zero + roli t2, t2, 8, dataSize=2 + or reg, t1, t2, dataSize=8 }; ''' -#let {{ -# class BSWAP(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; -- cgit v1.2.3