From f9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:45 -0800 Subject: X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0. --HG-- extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141 --- .../x86/isa/insts/general_purpose/data_conversion/sign_extension.py | 2 +- src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/isa/insts/general_purpose/data_conversion') diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py index 9a7c226af..ae3c6cc6f 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py @@ -55,7 +55,7 @@ microcode = ''' def macroop CDQE_R { - sext reg, reg, "env.dataSize << 2" + sexti reg, reg, "env.dataSize << 2 - 1" }; def macroop CQO_R_R { diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py index c2ccb9d19..d6ae7885a 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py @@ -55,7 +55,7 @@ microcode = ''' def macroop XLAT { - zext t1, rax, 8 + zexti t1, rax, 7 # Here, t1 can be used directly. The value of al is supposed to be treated # as unsigned. Since we zero extended it from 8 bits above and the address # size has to be at least 16 bits, t1 will not be sign extended. -- cgit v1.2.3