From f9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:45 -0800 Subject: X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0. --HG-- extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141 --- .../x86/isa/insts/general_purpose/data_transfer/stack_operations.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py') diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py index 5884d68c2..6c51f3171 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py @@ -162,9 +162,9 @@ def macroop ENTER_I_I { # Pull the different components out of the immediate limm t1, imm - zext t2, t1, 16, dataSize=2 + zexti t2, t1, 15, dataSize=2 srl t1, t1, 16 - zext t1, t1, 6 + zexti t1, t1, 5 # t1 is now the masked nesting level, and t2 is the amount of storage. # Push rbp. -- cgit v1.2.3