From f85cdccf4167180221fffddb9978bdb3953c1dc0 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Wed, 18 Sep 2019 16:50:19 -0700 Subject: arch-x86: Change warn to warn_once for NT instructions Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black Reviewed-by: Pouya Fotouhi Maintainer: Gabe Black Tested-by: kokoro --- .../x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/isa/insts/simd64/integer/data_transfer') diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py index ccd37f165..fdf303f37 100644 --- a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py @@ -38,12 +38,12 @@ microcode = ''' def macroop MOVNTQ_M_MMX { - warn "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!" + warn_once "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!" stfp mmx, seg, sib, "DISPLACEMENT", dataSize=8 }; def macroop MOVNTQ_P_MMX { - warn "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!" + warn_once "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!" rdip t7 stfp mmx, seg, riprel, "DISPLACEMENT", dataSize=8 }; -- cgit v1.2.3