From d86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 03:17:14 -0700
Subject: X86: Implement the load machine status word instruction (LMSW).

---
 src/arch/x86/isa/insts/system/control_registers.py | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)

(limited to 'src/arch/x86/isa/insts/system')

diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index 902c01abb..c09cdf6e8 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -32,4 +32,40 @@ def macroop CLTS {
     andi t1, t1, 0xF7, dataSize=1
     wrcr 0, t1, dataSize=8
 };
+
+def macroop LMSW_R {
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, reg, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_M {
+    ld t3, seg, sib, disp, dataSize=2
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, t3, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_P {
+    rdip t7, dataSize=asz
+    ld t3, seg, riprel, disp, dataSize=2
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, t3, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
 '''
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