From ea383880c61023360aee672c6197f2cda9889f07 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Mar 2018 17:41:15 -0700 Subject: x86: Implement the RDTSCP instruction. This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black --- src/arch/x86/isa/insts/system/msrs.py | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/arch/x86/isa/insts/system') diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index fe9c5b262..b79b6dbe9 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -66,4 +66,15 @@ def macroop RDTSC srli t1, t1, 32, dataSize=8 mov rdx, rdx, t1, dataSize=4 }; + +def macroop RDTSCP +{ + .serialize_before + mfence + rdtsc t1 + mov rax, rax, t1, dataSize=4 + srli t1, t1, 32, dataSize=8 + mov rdx, rdx, t1, dataSize=4 + rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4 +}; ''' -- cgit v1.2.3