From 2e4fb3f1390c2f6551817a99cd6e5329d6c28b25 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 1 Mar 2011 22:42:59 -0800 Subject: X86: Mark IO reads and writes as non-speculative. --- .../x86/isa/insts/general_purpose/input_output/general_io.py | 12 ++++++++---- .../x86/isa/insts/general_purpose/input_output/string_io.py | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) (limited to 'src/arch/x86/isa/insts') diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index 0674f0361..c034f8a48 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -42,22 +42,26 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) limm t1, imm, dataSize=asz - ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 - ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 - st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 + st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 - st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py index fee7b6599..3c90ee7e7 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py @@ -45,7 +45,8 @@ def macroop INS_M_R { zexti t2, reg, 15, dataSize=8 - ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True st t6, es, [1, t0, rdi] add rdi, rdi, t3, dataSize=asz @@ -63,7 +64,8 @@ def macroop INS_E_M_R { zexti t2, reg, 15, dataSize=8 topOfLoop: - ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True st t6, es, [1, t0, rdi] subi rcx, rcx, 1, flags=(EZF,), dataSize=asz @@ -83,7 +85,8 @@ def macroop OUTS_R_M { zexti t2, reg, 15, dataSize=8 ld t6, ds, [1, t0, rsi] - st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True add rsi, rsi, t3, dataSize=asz }; @@ -101,7 +104,8 @@ def macroop OUTS_E_R_M { topOfLoop: ld t6, ds, [1, t0, rsi] - st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 + st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ + nonSpec=True subi rcx, rcx, 1, flags=(EZF,), dataSize=asz add rsi, rsi, t3, dataSize=asz -- cgit v1.2.3