From 47bcc5c7379c7de677996ba8bfcd826d93459c09 Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <andreas@sandberg.pp.se>
Date: Mon, 30 Sep 2013 12:04:36 +0200
Subject: x86: Add support for FLDENV & FNSTENV

---
 .../control/save_and_restore_x87_environment.py    | 97 ++++++++++++++++++----
 1 file changed, 83 insertions(+), 14 deletions(-)

(limited to 'src/arch/x86/isa/insts')

diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
index babf942b9..44c44062b 100644
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
@@ -1,15 +1,6 @@
-# Copyright (c) 2007 The Hewlett-Packard Development Company
+# Copyright (c) 2013 Andreas Sandberg
 # All rights reserved.
 #
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met: redistributions of source code must retain the above copyright
@@ -33,10 +24,88 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Gabe Black
+# Authors: Andreas Sandberg
+
+
+# Register usage:
+#  t1, t2 == temporaries
+
+fldenvTemplate = """
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 0", dataSize=2
+    wrval fcw, t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2
+    wrval fsw, t1
+    srli t1, t1, 11, dataSize=2
+    andi t1, t1, 0x7, dataSize=2
+    wrval "InstRegIndex(MISCREG_X87_TOP)", t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2
+    wrval ftw, t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=4
+    wrval "InstRegIndex(MISCREG_FIOFF)", t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=2
+    wrval "InstRegIndex(MISCREG_FISEG)", t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 2", dataSize=2
+    wrval "InstRegIndex(MISCREG_FOP)", t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 20", dataSize=4
+    wrval "InstRegIndex(MISCREG_FOOFF)", t1
+
+    ld t1, seg, %(mode)s, "DISPLACEMENT + 24", dataSize=2
+    wrval "InstRegIndex(MISCREG_FOSEG)", t1
+"""
+
+fnstenvTemplate = """
+    rdval t2, fcw
+    st t2, seg, %(mode)s, "DISPLACEMENT + 0", dataSize=2
+
+    # FSW includes TOP when read
+    rdval t1, fsw
+    st t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2
+
+    rdval t1, ftw
+    st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2
+
+    rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+    st t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=4
+
+    rdval t1, "InstRegIndex(MISCREG_FISEG)"
+    st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=2
+
+    rdval t1, "InstRegIndex(MISCREG_FOP)"
+    st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 2", dataSize=2
+
+    rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+    st t1, seg, %(mode)s, "DISPLACEMENT + 20", dataSize=4
+
+    rdval t1, "InstRegIndex(MISCREG_FOSEG)"
+    st t1, seg, %(mode)s, "DISPLACEMENT + 24", dataSize=2
+
+    # Mask exceptions
+    ori t2, t2, 0x3F
+    wrval fcw, t2
+"""
 
 microcode = '''
-# FLDENV
-# FNSTENV
-# FSTENV
+def macroop FLDENV_M {
+''' + fldenvTemplate % { "mode" : "sib" } + '''
+};
+
+def macroop FLDENV_P {
+    rdip t7
+''' + fldenvTemplate % { "mode" : "riprel" } + '''
+};
+
+def macroop FNSTENV_M {
+''' + fnstenvTemplate % { "mode" : "sib" } + '''
+};
+
+def macroop FNSTENV_P {
+    rdip t7
+''' + fnstenvTemplate % { "mode" : "riprel" } + '''
+};
 '''
-- 
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