From aa7bc1be74beac674cc4feb4fece534de10379e3 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:17:14 -0800
Subject: X86: Implement the LTR instruction.

---
 src/arch/x86/isa/insts/system/segmentation.py | 48 +++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

(limited to 'src/arch/x86/isa/insts')

diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py
index 49d8eb110..c2bb46b7c 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -168,6 +168,54 @@ def macroop LIDT_16_P
     wrlimit idtr, t1
 };
 
+def macroop LTR_R
+{
+    chks reg, t0, TRCheck
+    limm t4, 0
+    srli t4, reg, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks reg, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, reg
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_M
+{
+    ld t5, seg, sib, disp, dataSize=2
+    chks t5, t0, TRCheck
+    limm t4, 0
+    srli t4, t5, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks t5, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, t5
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_P
+{
+    rdip t7
+    ld t5, seg, riprel, disp, dataSize=2
+    chks t5, t0, TRCheck
+    limm t4, 0
+    srli t4, t5, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks t5, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, t5
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
 def macroop SWAPGS
 {
     rdval t1, kernel_gs_base, dataSize=8
-- 
cgit v1.2.3