From d8494325f07695e810e51dffbf9daf5145b10d1a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 19 Oct 2007 15:21:16 -0700
Subject: X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions.

--HG--
extra : convert_revision : 37c63b1133022fa3432888592f8c84785fb95091
---
 .../insts/general_purpose/flags/load_and_store.py  | 32 +++++++++++++++-----
 .../insts/general_purpose/flags/push_and_pop.py    | 34 ++++++++++++----------
 2 files changed, 44 insertions(+), 22 deletions(-)

(limited to 'src/arch/x86/isa/insts')

diff --git a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
index c6f279a25..0915bf819 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
@@ -53,10 +53,28 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class LAHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SAHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SAHF {
+    # This will fold to ah since this never executes in 64 bit mode.
+    ruflags rsp, dataSize=1
+};
+
+# This is allows the instruction to write to ah in 64 bit mode.
+def macroop SAHF_64 {
+    ruflags t1
+    slli t1, t1, 8
+    mov t1, t1, rax, dataSize=1
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop LAHF {
+    # This will fold to ah since this never executes in 64 bit mode.
+    wruflags rsp, t0, dataSize=1
+};
+
+# This is allows the instruction to read from ah in 64 bit mode.
+def macroop LAHF_64 {
+    srli t1, rax, 8, dataSize=2
+    wruflags t1, t0, dataSize=1
+};
+'''
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
index dbb6c34c4..87e9ef03a 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
@@ -53,18 +53,22 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class POPF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPFD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPFQ(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHFD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class pushfq(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop PUSHF {
+    .adjust_env oszIn64Override
+
+    # This should really read the whole flags register, not just user flags.
+    ruflags t1
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
+    subi rsp, rsp, dsz
+};
+
+def macroop POPF {
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [1, t0, rsp]
+    addi rsp, rsp, dsz
+    # This should really write the whole flags register, not just user flags.
+    wruflags t1, t0
+};
+'''
-- 
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