From a2e0d539d89643ce5243be9b8a0be4c3bcee7520 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 22:55:55 -0700
Subject: X86: Add wrval/rdval microops for reading significant miscregs.

---
 src/arch/x86/isa/microasm.isa | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/arch/x86/isa/microasm.isa')

diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 81aa1dafe..f9e0a2fa8 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -159,6 +159,11 @@ let {{
     assembler.symbols["CTrue"] = "ConditionTests::True"
     assembler.symbols["CFalse"] = "ConditionTests::False"
 
+    for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
+                'star', 'lstar', 'cstar', 'sf_mask',
+                'kernel_gs_base'):
+        assembler.symbols[reg] = "MISCREG_%s" % reg.upper()
+
     # Code literal which forces a default 64 bit operand size in 64 bit mode.
     assembler.symbols["oszIn64Override"] = '''
     if (machInst.mode.submode == SixtyFourBitMode &&
-- 
cgit v1.2.3