From b64d0bdeda1662091746c3695b4429fcc6f69342 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 5 Aug 2009 03:07:01 -0700
Subject: X86: Fix condition code setting for signed multiplies with negative
 results.

---
 src/arch/x86/isa/microops/regop.isa | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

(limited to 'src/arch/x86/isa/microops/regop.isa')

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index f2e16a515..6921684a4 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -536,6 +536,14 @@ let {{
                 hiResult -= psrc1;
             ProdHi = hiResult;
             '''
+        flag_code = '''
+            if ((-ProdHi & mask(dataSize * 8)) !=
+                    bits(ProdLow, dataSize * 8 - 1)) {
+                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
+            } else {
+                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
+            }
+        '''
 
     class Mul1u(WrRegOp):
         code = '''
@@ -550,6 +558,13 @@ let {{
                       ((psrc1_l * psrc2_l) / shifter)) / shifter) +
                      psrc1_h * psrc2_h;
             '''
+        flag_code = '''
+            if (ProdHi) {
+                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
+            } else {
+                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
+            }
+        '''
 
     class Mulel(RdRegOp):
         code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
@@ -561,12 +576,6 @@ let {{
             super(RdRegOp, self).__init__(dest, src1, \
                     "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
-        flag_code = '''
-            if (ProdHi)
-                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
-            else
-                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
-        '''
 
     # One or two bit divide
     class Div1(WrRegOp):
-- 
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