From 4d4d212ae974b3a3ad6d185902d4896c0233a8d9 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 22 May 2012 11:29:53 -0500 Subject: X86: Split Condition Code register This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch. --- src/arch/x86/isa/microops/specop.isa | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/x86/isa/microops/specop.isa') diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 5c242e2c9..8092b28b9 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -181,7 +181,8 @@ let {{ iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase", {"code": "", - "cond_test": "checkCondition(ccFlagBits, cc)"}) + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + ecfBit | ezfBit, cc)"}) exec_output = MicroFaultExecute.subst(iop) header_output = MicroFaultDeclare.subst(iop) decoder_output = MicroFaultConstructor.subst(iop) -- cgit v1.2.3