From 83f2b253989fd6dfc8f48d5368ae351ade91cfc6 Mon Sep 17 00:00:00 2001 From: Swapnil Haria Date: Mon, 15 Jan 2018 21:49:17 -0600 Subject: arch-x86: Adding clflush, clflushopt, clwb instructions This patch adds support for cache flushing instructions in x86. It piggybacks on support for similar instructions in arm ISA added by Nikos Nikoleris. I have tested each instruction using microbenchmarks. Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d Reviewed-on: https://gem5-review.googlesource.com/7401 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/arch/x86/isa/microops/ldstop.isa | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/arch/x86/isa/microops') diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index a3d9c5a70..83e24e154 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -634,6 +634,11 @@ let {{ ''') defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") + defineMicroStoreOp('Clflushopt', 'Mem = 0;', + mem_flags="Request::CLEAN | Request::INVALIDATE" + + " | Request::DST_POC") + defineMicroStoreOp('Clwb', 'Mem = 0;', + mem_flags="Request::CLEAN | Request::DST_POC") def defineMicroStoreSplitOp(mnemonic, code, completeCode="", mem_flags="0"): -- cgit v1.2.3