From 8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 4 Sep 2007 23:32:18 -0700 Subject: X86: Add some SSE floating point/integer conversion microops. --HG-- extra : convert_revision : 2a1aa16709db940f5f40bbd84ca082f26b03b9c5 --- src/arch/x86/isa/microops/regop.isa | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/arch/x86/isa/microops') diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index e169b09d2..3641438f5 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -636,4 +636,23 @@ let {{ class Zext(RegOp): code = 'DestReg = bits(psrc1, imm8-1, 0);' + + # Conversion microops + class ConvOp(RegOp): + abstract = True + def __init__(self, dest, src1): + super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS") + + #FIXME This needs to always use 32 bits unless REX.W is present + class cvtf_i2d(ConvOp): + code = 'FpDestReg = psrc1;' + + class cvtf_i2d_hi(ConvOp): + code = 'FpDestReg = bits(SrcReg1, 63, 32);' + + class cvtf_d2i(ConvOp): + code = ''' + int64_t intSrcReg1 = static_cast(FpSrcReg1); + DestReg = merge(DestReg, intSrcReg1, dataSize); + ''' }}; -- cgit v1.2.3