From d3e021820eb9916d63b96ba732ccc0783626433b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Dec 2010 00:27:23 -0800
Subject: X86: Take advantage of new PCState syntax.

---
 src/arch/x86/isa/microops/regop.isa | 13 +++----------
 src/arch/x86/isa/microops/seqop.isa | 16 ++++------------
 2 files changed, 7 insertions(+), 22 deletions(-)

(limited to 'src/arch/x86/isa/microops')

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 86ebac174..975bdce8a 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -944,12 +944,8 @@ let {{
         code = 'DoubleBits = psrc1 ^ op2;'
 
     class Wrip(WrRegOp, CondRegOp):
-        code = '''
-        X86ISA::PCState pc = PCS;
-        pc.npc(psrc1 + sop2 + CSBase);
-        PCS = pc;
-        '''
-        else_code = "PCS = PCS;"
+        code = 'NRIP = psrc1 + sop2 + CSBase;'
+        else_code = "NRIP = NRIP;"
 
     class Wruflags(WrRegOp):
         code = 'ccFlagBits = psrc1 ^ op2'
@@ -965,10 +961,7 @@ let {{
         '''
 
     class Rdip(RdRegOp):
-        code = '''
-        X86ISA::PCState pc = PCS;
-        DestReg = pc.npc() - CSBase;
-        '''
+        code = 'DestReg = NRIP - CSBase;'
 
     class Ruflags(RdRegOp):
         code = 'DestReg = ccFlagBits'
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index a3e22b0aa..1b125ec9c 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -169,23 +169,15 @@ let {{
             return super(Eret, self).getAllocator(microFlags)
 
     iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
-            {"code": '''
-             X86ISA::PCState pc = PCS;
-             pc.nupc(target);
-             PCS = pc;
-             ''',
-             "else_code": "PCS = PCS",
+            {"code": "nuIP = target;",
+             "else_code": "nuIP = nuIP;",
              "cond_test": "checkCondition(ccFlagBits, cc)"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
     decoder_output += SeqOpConstructor.subst(iop)
     iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
-            {"code": '''
-             X86ISA::PCState pc = PCS;
-             pc.nupc(target);
-             PCS = pc;
-             ''',
-             "else_code": "PCS = PCS",
+            {"code": "nuIP = target;",
+             "else_code": "nuIP = nuIP;",
              "cond_test": "true"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
-- 
cgit v1.2.3