From 4e3ff42762f8fd08e130b10e59525139f12c932d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 1 Dec 2007 23:00:58 -0800 Subject: X86: Implement wrbase and wrlimit for loading pseudo descriptors. --HG-- extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02 --- src/arch/x86/isa/operands.isa | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/x86/isa/operands.isa') diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 7a2631a9c..fff60ce60 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -127,5 +127,8 @@ def operands {{ 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73), 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74), 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), + 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75), + 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76), + 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; -- cgit v1.2.3