From fd77212b72427f57a800fceface8a85a5b5e4001 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 29 Mar 2007 00:49:53 -0700
Subject: Add code to generate register and immediate based integer op microop
 classes.

--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
---
 src/arch/x86/isa/operands.isa | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/arch/x86/isa/operands.isa')

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 20376f38f..36b0ee4df 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
 }};
 
 def operands {{
-        # This is just copied from SPARC, because having no operands confuses
-        # the parser.
-        'Rd':               ('IntReg', 'udw', 'RD', 'IsInteger', 1)
+        'IntRegOp0':     ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
+        'IntRegOp1':     ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
+        'IntRegOp2':     ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
 }};
-- 
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