From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001
From: Nathanael Premillieu <nathanael.premillieu@arm.com>
Date: Wed, 5 Apr 2017 12:46:06 -0500
Subject: arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
---
 src/arch/x86/isa/microops/limmop.isa |  2 +-
 src/arch/x86/isa/specialize.isa      | 25 ++++++++++++++++++++-----
 2 files changed, 21 insertions(+), 6 deletions(-)

(limited to 'src/arch/x86/isa')

diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index cd282f67a..8a832f5d5 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -95,7 +95,7 @@ def template MicroLimmOpConstructor {{
             InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 setFlags, %(op_class)s),
-                dest(_dest.idx), imm(_imm), dataSize(_dataSize)
+                dest(_dest.regIdx), imm(_imm), dataSize(_dataSize)
     {
         foldOBit = (dataSize == 1 && !machInst.rex.present) ? 1 << 6 : 0;
         %(constructor)s;
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 5a21c0944..84e5f6b02 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -143,13 +143,19 @@ let {{
                     regString = "INTREG_R%s" % opType.reg
                 env.addReg(regString)
                 env.addToDisassembly(
-                        "printReg(out, %s, regSize);\n" % regString)
+                    "printReg(out, InstRegIndex(%s), regSize);\n" %
+                                                                     regString)
+
                 Name += "_R"
+
             elif opType.tag == "B":
                 # This refers to registers whose index is encoded as part of the opcode
                 env.addToDisassembly(
-                        "printReg(out, %s, regSize);\n" % InstRegIndex)
+                        "printReg(out, InstRegIndex(%s), regSize);\n" %
+                                                                  InstRegIndex)
+
                 Name += "_R"
+
                 env.addReg(InstRegIndex)
             elif opType.tag == "M":
                 # This refers to memory. The macroop constructor sets up modrm
@@ -182,8 +188,11 @@ let {{
                 # Use the "reg" field of the ModRM byte to select the register
                 env.addReg(ModRMRegIndex)
                 env.addToDisassembly(
-                        "printReg(out, %s, regSize);\n" % ModRMRegIndex)
+                        "printReg(out, InstRegIndex(%s), regSize);\n" %
+                                                                 ModRMRegIndex)
+
                 if opType.tag == "P":
+
                     Name += "_MMX"
                 elif opType.tag == "V":
                     Name += "_XMM"
@@ -195,8 +204,11 @@ let {{
                 regEnv = copy.copy(env)
                 regEnv.addReg(ModRMRMIndex)
                 regEnv.addToDisassembly(
-                        "printReg(out, %s, regSize);\n" % ModRMRMIndex)
+                        "printReg(out, InstRegIndex(%s), regSize);\n" %
+                                                                  ModRMRMIndex)
+
                 # This refers to memory. The macroop constructor should set up
+
                 # modrm addressing.
                 memEnv = copy.copy(env)
                 memEnv.doModRM = True
@@ -222,8 +234,11 @@ let {{
                 # Non register modrm settings should cause an error
                 env.addReg(ModRMRMIndex)
                 env.addToDisassembly(
-                        "printReg(out, %s, regSize);\n" % ModRMRMIndex)
+                        "printReg(out, InstRegIndex(%s), regSize);\n" %
+                                                                  ModRMRMIndex)
+
                 if opType.tag == "PR":
+
                     Name += "_MMX"
                 elif opType.tag == "VR":
                     Name += "_XMM"
-- 
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