From bdd55ec8b6eda4b46288d8f85a5a9fa603cd6ab4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Apr 2009 03:22:38 -0700 Subject: X86: Implement the save machine status word instruction (SMSW). --- src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++-- src/arch/x86/isa/insts/system/control_registers.py | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/isa') diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index e55756fec..c344ee550 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -125,7 +125,7 @@ 0x6: skinit(); 0x7: invlpga(); } - 0x4: smsw_Rv(); + 0x4: Inst::SMSW(Rv); 0x6: Inst::LMSW(Rv); 0x7: decode MODRM_RM { 0x0: Inst::SWAPGS(); @@ -155,7 +155,7 @@ default: Inst::LIDT(M); } } - 0x4: smsw_Mw(); + 0x4: Inst::SMSW(Mw); 0x6: Inst::LMSW(Mw); 0x7: Inst::INVLPG(M); default: Inst::UD2(); diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py index c09cdf6e8..82811bb07 100644 --- a/src/arch/x86/isa/insts/system/control_registers.py +++ b/src/arch/x86/isa/insts/system/control_registers.py @@ -68,4 +68,19 @@ def macroop LMSW_P { or t1, t1, t2, dataSize=8 wrcr 0, t1, dataSize=8 }; + +def macroop SMSW_R { + rdcr reg, 0 +}; + +def macroop SMSW_M { + rdcr t1, 0 + st t1, seg, sib, disp, dataSize=2 +}; + +def macroop SMSW_P { + rdcr t1, 0 + rdip t7, dataSize=asz + st t1, seg, riprel, disp, dataSize=2 +}; ''' -- cgit v1.2.3