From 05c86ec0d7662ccefc5690a4445fcf2976d16622 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 6 Mar 2007 15:42:30 +0000
Subject: Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
    Add in process source files.
src/arch/x86/isa_traits.hh:
    Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
    Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
    An X86 process class.
src/base/loader/elf_object.cc:
    Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
    Add an x86 traceflag
src/sim/process.cc:
    Add in code to create an x86 process.
src/arch/x86/intregs.hh:
    A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
    A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
    An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
    The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
    The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
    An x86 hello world test binary.

--HG--
extra : convert_revision : f22919e010c07aeaf5757dca054d9877a537fd08
---
 src/arch/x86/isa_traits.hh | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

(limited to 'src/arch/x86/isa_traits.hh')

diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index d5da8b420..5a625f741 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -58,6 +58,7 @@
 #ifndef __ARCH_X86_ISATRAITS_HH__
 #define __ARCH_X86_ISATRAITS_HH__
 
+#include "arch/x86/intregs.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
 
@@ -93,21 +94,21 @@ namespace X86ISA
     // semantically meaningful register indices
     //There is no such register in X86
     const int ZeroReg = 0;
-    const int StackPointerReg = 4; //RSP
+    const int StackPointerReg = INTREG_RSP;
     //X86 doesn't seem to have a link register
     const int ReturnAddressReg = 0;
-    const int ReturnValueReg = 0; //RAX
-    const int FramePointerReg = 5; //RBP
-    const int ArgumentReg0 = 7; //RDI
-    const int ArgumentReg1 = 6; //RSI
-    const int ArgumentReg2 = 2; //RDX
-    const int ArgumentReg3 = 1; //RCX
-    const int ArgumentReg4 = 8; //R8W
-    const int ArgumentReg5 = 9; //R9W
+    const int ReturnValueReg = INTREG_RAX;
+    const int FramePointerReg = INTREG_RBP;
+    const int ArgumentReg0 = INTREG_RDI;
+    const int ArgumentReg1 = INTREG_RSI;
+    const int ArgumentReg2 = INTREG_RDX;
+    const int ArgumentReg3 = INTREG_RCX;
+    const int ArgumentReg4 = INTREG_R8W;
+    const int ArgumentReg5 = INTREG_R9W;
 
     // Some OS syscalls use a second register (rdx) to return a second
     // value
-    const int SyscallPseudoReturnReg = 2; //RDX
+    const int SyscallPseudoReturnReg = INTREG_RDX;
 
     //XXX These numbers are bogus
     const int MaxInstSrcRegs = 10;
-- 
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