From d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 09:09:56 -0700
Subject: Turn Interrupts objects into SimObjects. Also, move local APIC state
 into x86's Interrupts object.

---
 src/arch/x86/miscregs.hh | 59 ++++++++----------------------------------------
 1 file changed, 9 insertions(+), 50 deletions(-)

(limited to 'src/arch/x86/miscregs.hh')

diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 5a6ee752d..dbf08ec5d 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -58,6 +58,7 @@
 #ifndef __ARCH_X86_MISCREGS_HH__
 #define __ARCH_X86_MISCREGS_HH__
 
+#include "arch/x86/apicregs.hh"
 #include "arch/x86/segmentregs.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitunion.hh"
@@ -368,39 +369,9 @@ namespace X86ISA
 
         MISCREG_APIC_BASE,
 
+        // Space for the APIC registers
         MISCREG_APIC_START,
-        MISCREG_APIC_ID = MISCREG_APIC_START,
-        MISCREG_APIC_VERSION,
-        MISCREG_APIC_TASK_PRIORITY,
-        MISCREG_APIC_ARBITRATION_PRIORITY,
-        MISCREG_APIC_PROCESSOR_PRIORITY,
-        MISCREG_APIC_EOI,
-        MISCREG_APIC_LOGICAL_DESTINATION,
-        MISCREG_APIC_DESTINATION_FORMAT,
-        MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
-
-        MISCREG_APIC_IN_SERVICE_BASE,
-
-        MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
-
-        MISCREG_APIC_INTERRUPT_REQUEST_BASE =
-            MISCREG_APIC_TRIGGER_MODE_BASE + 16,
-
-        MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
-        MISCREG_APIC_INTERRUPT_COMMAND_LOW,
-        MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
-        MISCREG_APIC_LVT_TIMER,
-        MISCREG_APIC_LVT_THERMAL_SENSOR,
-        MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
-        MISCREG_APIC_LVT_LINT0,
-        MISCREG_APIC_LVT_LINT1,
-        MISCREG_APIC_LVT_ERROR,
-        MISCREG_APIC_INITIAL_COUNT,
-        MISCREG_APIC_CURRENT_COUNT,
-        MISCREG_APIC_DIVIDE_CONFIGURATION,
-        MISCREG_APIC_END = MISCREG_APIC_DIVIDE_CONFIGURATION,
-
-        MISCREG_APIC_INTERNAL_STATE,
+        MISCREG_APIC_END = MISCREG_APIC_START + NUM_APIC_REGS - 1,
 
         // "Fake" MSRs for internally implemented devices
         MISCREG_PCI_CONFIG_ADDRESS,
@@ -408,6 +379,12 @@ namespace X86ISA
         NUM_MISCREGS
     };
 
+    static inline bool
+    isApicReg(MiscRegIndex index)
+    {
+        return index >= MISCREG_APIC_START && index <= MISCREG_APIC_END;
+    }
+
     static inline MiscRegIndex
     MISCREG_CR(int index)
     {
@@ -510,24 +487,6 @@ namespace X86ISA
         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
     }
 
-    static inline MiscRegIndex
-    MISCREG_APIC_IN_SERVICE(int index)
-    {
-        return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
-    }
-
-    static inline MiscRegIndex
-    MISCREG_APIC_TRIGGER_MODE(int index)
-    {
-        return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
-    }
-
-    static inline MiscRegIndex
-    MISCREG_APIC_INTERRUPT_REQUEST(int index)
-    {
-        return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
-    }
-
     /**
      * A type to describe the condition code bits of the RFLAGS register,
      * plus two flags, EZF and ECF, which are only visible to microcode.
-- 
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