From 911ccef6c05fff4832245414baa7b2a67955c35a Mon Sep 17 00:00:00 2001
From: Joel Hestness <hestness@cs.utexas.edu>
Date: Sun, 6 Feb 2011 22:14:17 -0800
Subject: x86: Add checkpointing capability to arch components

Add checkpointing capability to the x86 interrupt device and the TLBs
---
 src/arch/x86/pagetable.cc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/arch/x86/pagetable.cc')

diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc
index 6de4c956f..a7717def7 100644
--- a/src/arch/x86/pagetable.cc
+++ b/src/arch/x86/pagetable.cc
@@ -52,11 +52,29 @@ TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) :
 void
 TlbEntry::serialize(std::ostream &os)
 {
+    SERIALIZE_SCALAR(paddr);
+    SERIALIZE_SCALAR(vaddr);
+    SERIALIZE_SCALAR(size);
+    SERIALIZE_SCALAR(writable);
+    SERIALIZE_SCALAR(user);
+    SERIALIZE_SCALAR(uncacheable);
+    SERIALIZE_SCALAR(global);
+    SERIALIZE_SCALAR(patBit);
+    SERIALIZE_SCALAR(noExec);
 }
 
 void
 TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
 {
+    UNSERIALIZE_SCALAR(paddr);
+    UNSERIALIZE_SCALAR(vaddr);
+    UNSERIALIZE_SCALAR(size);
+    UNSERIALIZE_SCALAR(writable);
+    UNSERIALIZE_SCALAR(user);
+    UNSERIALIZE_SCALAR(uncacheable);
+    UNSERIALIZE_SCALAR(global);
+    UNSERIALIZE_SCALAR(patBit);
+    UNSERIALIZE_SCALAR(noExec);
 }
 
 }
-- 
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