From b904bd5437ead0dfc2c4c0977f3d29d63299c601 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Fri, 15 Feb 2013 17:40:09 -0500 Subject: sim: Add a system-global option to bypass caches Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches. To make memory mode tests cleaner, the following methods are added to the System class: * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed. The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore. --- src/arch/x86/pagetable_walker.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/x86/pagetable_walker.cc') diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 1e42e5593..b096fbfe8 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -88,7 +88,7 @@ Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation, // outstanding requests, see if this request can be coalesced with // another one (i.e. either coalesce or start walk) WalkerState * newState = new WalkerState(this, _translation, _req); - newState->initState(_tc, _mode, sys->getMemoryMode() == Enums::timing); + newState->initState(_tc, _mode, sys->isTimingMode()); if (currStates.size()) { assert(newState->isTiming()); DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size()); -- cgit v1.2.3