From 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:12:35 -0400 Subject: Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. --- src/arch/x86/pagetable_walker.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/x86/pagetable_walker.hh') diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index c59661619..07f476b00 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -169,7 +169,8 @@ namespace X86ISA RequestPtr req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode); - MasterPort &getMasterPort(const std::string &if_name, int idx = -1); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); protected: // The TLB we're supposed to load. -- cgit v1.2.3